scholarly journals 2-nm laser-synthesized Si nanoparticles for low-power charge trapping memory devices

2014 ◽  
Author(s):  
Nazek El-Atab ◽  
Ayse Ozcan ◽  
Sabri Alkis ◽  
Ali K. Okyay ◽  
Ammar Nayfeh
Keyword(s):  
Low Power ◽  
Charge Trapping ◽  
Memory Devices ◽  
Si Nanoparticles ◽  
Charge Trapping Memory

scholarly journals Low power zinc-oxide based charge trapping memory with embedded silicon nanoparticles via poole-frenkel hole emission

2014 ◽  
Vol 104 (1) ◽  
pp. 013112 ◽  
Author(s):  
Nazek El-Atab ◽  
Ayse Ozcan ◽  
Sabri Alkis ◽  
Ali K. Okyay ◽  
Ammar Nayfeh
Keyword(s):  
Zinc Oxide ◽  
Low Power ◽  
Silicon Nanoparticles ◽  
Charge Trapping ◽  
Charge Trapping Memory

Enhanced charge storage performance in AlTi4Ox/Al2O3multilayer charge trapping memory devices

2014 ◽  
Vol 53 (8S3) ◽  
pp. 08NG02 ◽  
Author(s):  
Changjie Gong ◽  
Xin Ou ◽  
Bo Xu ◽  
Xuexin Lan ◽  
Yan Lei ◽  
...  
Keyword(s):  
Charge Trapping ◽  
Charge Storage ◽  
Memory Devices ◽  
Storage Performance ◽  
Charge Trapping Memory

scholarly journals The effect of the thickness of tunneling layer on the memory properties of (Cu2O)0.5(Al2O3)0.5 high-k composite charge-trapping memory devices

2016 ◽  
Vol 30 (15) ◽  
pp. 1650279 ◽  
Author(s):  
Jinqiu Liu ◽  
Jianxin Lu ◽  
Jiang Yin ◽  
Bo Xu ◽  
Yidong Xia ◽  
...  
Keyword(s):  
Magnetron Sputtering ◽  
Charge Trapping ◽  
Atomic Layer ◽  
Rf Magnetron Sputtering ◽  
Memory Devices ◽  
Layer Deposition ◽  
High K ◽  
Charge Trapping Memory ◽  
Deposition Techniques ◽  
Composite Charge

The charge-trapping memory devices namely Pt/Al2O3/(Al2O[Formula: see text](Cu2O)[Formula: see text]/SiO2/[Formula: see text]-Si with 2, 3 and 4 nm SiO2 tunneling layers were fabricated by using RF magnetron sputtering and atomic layer deposition techniques. At an applied voltage of ±11 V, the memory windows in the C–V curves of the memory devices with 2, 3 and 4 nm SiO2 tunneling layers were about 4.18, 9.91 and 11.33 V, respectively. The anomaly in memory properties among the three memory devices was ascribed to the different back tunneling probabilities of trapped electrons in the charge-trapping dielectric (Al2O[Formula: see text](Cu2O)[Formula: see text] due to the different thicknesses of SiO2 tunneling layer.

scholarly journals Charge Trapping Memory with 2.85-nm Si-Nanoparticles Embedded in HfO2

2015 ◽  
Vol 66 (40) ◽  
pp. 17-21
Author(s):  
N. El-Atab ◽  
B. B. Turgut ◽  
A. Okyay ◽  
A. Nayfeh
Keyword(s):  
Charge Trapping ◽  
Si Nanoparticles ◽  
Charge Trapping Memory

Novel Dual Bit Tri-Gate Charge Trapping Memory Devices

2004 ◽  
Vol 25 (12) ◽  
pp. 810-812 ◽  
Author(s):  
M. Specht ◽  
R. Kommling ◽  
F. Hofmann ◽  
V. Klandzievski ◽  
L. Dreeskornfeld ◽  
...  
Keyword(s):  
Charge Trapping ◽  
Memory Devices ◽  
Charge Trapping Memory ◽  
Gate Charge
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