SiC Fin-Shaped Gate Trench MOSFET with Integrated Schottky Diode

A silicon carbide (SiC) trench MOSFET featuring fin-shaped gate and integrated Schottky barrier diode under split P type shield (SPS) protection (FS-TMOS) is proposed by finite element modeling. The physical mechanism of FS-TMOS is studied comprehensively in terms of fundamental (blocking, conduction, and dynamic) performance and transient extreme stress reliability. The fin-shaped gate on the sidewall of the trench and integrated Schottky diode at the bottom of trench aim to the reduction of gate charge and improvement on the third quadrant performance, respectively. The SPS region is fully utilized to suppress excessive electric field both at trench oxide and Schottky contact when OFF-state. Compared with conventional trench MOSFET (C-TMOS), the gate charge, Miller charge, Von at third quadrant, Ron,sp·Qgd, and Ron,sp·Qg of FS-TMOS are significantly reduced by 34%, 20%, 65%, 0.1%, and 14%, respectively. Furthermore, short-circuit and avalanche capabilities are discussed, verifying the FS-TMOS is more robust than C-TMOS. It suggests that the proposed FS-TMOS is a promising candidate for next-generation high efficiency and high-power density applications.

A Charge Balanced Vertical Power MOSFET With Record High Balliga’s Figure of Merit: Design and Investigation

In this work, we design and simulate a high-performance vertical power MOSFET with a charge balanced drift layer, which modulates the RON-BV relation from super quadratic to linear. The proposed device is designed with a super junction drift layer which modulates the RON-BV relation from super quadratic to linear. The proposed device has the source and channel regions isolated from the super junction drift layer. This results in a significant improvement in the performance of the proposed device in comparison to the other conventional devices, in terms of Balliga’s figure of merit. A 2D TCAD simulation study reveals that the proposed device with an epitaxial layer thickness of 50μm shows an ON resistance of 3.84mΩ.cm2 for a break down voltage of 833V, which is the lowest among the resistances reported in the previous literature at this breakdown voltage. Further, the study of charge imbalances and the capacitance analyses including the calculation of gate charge has also been done. The values of Balliga’s figure of merit (FOM) calculated for all the drift thicknesses of the proposed structures are significantly outperforming the conventional super junction structures reported so far.