Improving the Partial Product Tree Compression on Signed Radix-2m Parallel Multipliers

Author(s):  
Leandro M. G. Rocha ◽  
Morgana Macedo ◽  
Guilherme Paim ◽  
Eduardo Costa ◽  
Sergio Bampi
1997 ◽  
Vol 32 (3) ◽  
pp. 468-476 ◽  
Author(s):  
Jun Rim Choi ◽  
Lak Hyun Jang ◽  
Seong Wook Jung ◽  
Jin Ho Choi

1970 ◽  
Vol 48 (11) ◽  
pp. 1782-1785 ◽  
Author(s):  
P. R. McLean ◽  
D. J. McKenney

Rates of formation of ethylene, hydrogen, and methane have been measured at 630 °C for the thermal decomposition of ethane at pressures between 100 and 620 Torr, with various pressures (approximately 1 to 100 Torr) of added hydrogen sulfide. The effect of the H2S was to increase the rate of methane formation and to decrease the rate of ethylene and hydrogen formation. Rates of formation of all three of these gases decreased with increasing hydrogen sulfide pressures. The quantitative data obtained and the partial product analysis indicate that a complex mechanism is operative. Possible qualitative explanations for the observations are discussed.


Author(s):  
Georgios Zervakis ◽  
Kostas Tsoumanis ◽  
Sotirios Xydis ◽  
Nicholas Axelos ◽  
Kiamal Pekmestzi
Keyword(s):  

Author(s):  
Sachin B. Jadhav ◽  
Jayamala K. Patil ◽  
Ramesh T. Patil

This paper presents the details of hardware implementation of modified partial product reduction tree using 4:2 and 5:2 compressors. Speed of multiplication operation is improved by using higher compressors .In order to improve the speed of the multiplication process within the computational unit; there is a major bottleneck that is needed to be considered that is the partial products reduction network which is used in the multiplication block. For implementation of this stage require addition of large operands that involve long paths for carry propagation. The proposed architecture is based on binary tree constructed using modified 4:2 and 5:2 compressor circuits. Increasing the speed of operation is achieved by using higher modified compressors in critical path. Our objective of work is, to increase the speed of multiplication operation by minimizing the number of combinational gates using higher n:2 compressors. The experimental test of the proposed modified compressor is done using Spartan-3FPGA device (XC3S400 PQ-208). Using tree architectures for the partial products reduction network represent an attractive solution that is frequently applied to speed up the multiplication process. The simulation result shows 4:2 and 5:2 compressor output which is done using Questa Sim 6.4c Mentor Graphics tool.


1908 ◽  
Vol 4 (74) ◽  
pp. 321-322
Author(s):  
A. S. Grant

So-called “standard form.”Method I have used with success as regards clearness and accuracy. (I believe this is Mr. Pendlebury’s arrangement.)Ride. Put singles (or units) figure of multiplier under the last figure of multiplicand.Arguments in favour of this second plan :Instead of such a mechanical rule as Mr. Borchardt’s (p. 69, Borchardt’s ,Arithmetical Types and Examples), we get the continued use of the sound and fundamental rule of “putting each first figure of a partial product underneath the figure to which that partial product is due.” And this also corresponds to the method of algebraic multiplication.


2020 ◽  
Vol 100 ◽  
pp. 104778 ◽  
Author(s):  
S. Tabrizchi ◽  
R. Akbar ◽  
F. Safaei
Keyword(s):  

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