A 10b SAR ADC with Widely Scalable Sampling Rate and AGC Amplifier Front-End

Author(s):  
Ayca Akkaya ◽  
Firat Celik ◽  
Armin Tajalli ◽  
Yusuf Leblebici
Keyword(s):  
Sar Adc ◽  
Electronics ◽  
2020 ◽  
Vol 9 (7) ◽  
pp. 1100
Author(s):  
Deeksha Verma ◽  
Khuram Shehzad ◽  
Danial Khan ◽  
Sung Jin Kim ◽  
Young Gun Pu ◽  
...  

A design of low-power 10-bit 1 MS/s asynchronous successive approximation register analog-to-digital converter (SAR ADC) is presented in this paper. To improve the linearity of the digital-to-analog converter (DAC) and energy efficiency, a common mode-based monotonic charge recovery (CMMC) switching technique is proposed. The proposed switching technique consumes only 63.75 CVREF2 switching energy, which is far less as compared to the conventional switching technique without dividing or adding additional switches. In addition, bootstrap switching is implemented to ensure enhanced linearity. To reduce the power consumption from the comparator, a dynamic latch comparator with a self-comparator clock generation circuit is implemented. The proposed prototype of the SAR ADC is implemented in a 55 nm CMOS (complementary metal-oxide-semiconductor) process. The proposed architecture achieves a figure of merit (FOM) of 17.4 fJ/conversion, signal-to-noise distortion ratio (SNDR) of 60.39 dB, and an effective number of bits (ENOB) of 9.74 bits with a sampling rate of 1 MS/s at measurement levels. The implemented SAR ADC consumes 14.8 µW power at 1 V power supply.


Author(s):  
M. De Matteis ◽  
A. Pezzotta ◽  
M. Sabatini ◽  
M. Grassi ◽  
M. Croce ◽  
...  
Keyword(s):  
Sar Adc ◽  

2017 ◽  
Vol 92 (3) ◽  
pp. 453-465 ◽  
Author(s):  
M. De Matteis ◽  
A. Pezzotta ◽  
M. Sabatini ◽  
M. Grassi ◽  
M. Croce ◽  
...  

Author(s):  
Takatsugu Kamata ◽  
Masayuki Ueda ◽  
Yusaku Hirai ◽  
Sadahiro Tani ◽  
Tomohiro Asano ◽  
...  

2016 ◽  
Vol 37 (1) ◽  
pp. 015005
Author(s):  
Wei Liu ◽  
Tingcun Wei ◽  
Bo Li ◽  
Lifeng Yang ◽  
Yongcai Hu

Electronics ◽  
2021 ◽  
Vol 10 (16) ◽  
pp. 1968
Author(s):  
Juyong Lee ◽  
Seungjun Lee ◽  
Kihyun Kim ◽  
Hyungil Chae

In this study, a pipelined noise-shaping successive-approximation register analog-to-digital converter (PLNS-SAR ADC) structure was proposed to achieve high resolution and to be free from comparator design requirements. The inter-stage amplifier and integrator of the PLNS-SAR ADC were implemented through a ring amplifier with high gain and speed. The ring amplifier was designed to improve power efficiency and be tolerant to process–voltage–temperature (PVT) variation, and uses a single loop common-mode feedback (CMFB) circuit. By processing residual signals with a single ring amplifier, power efficiency can be maximized, and a low-power system with 30% lower power consumption than that of a conventional PLNS-SAR ADC is implemented. With a high-gain ring amplifier, noise leakage is greatly suppressed, and a structure can be implemented that is tolerant of mismatches between the analog loop and digital correction filters. The measured signal to noise distortion ratio (SNDR) is 70 dB for a 5.15 MHz bandwidth (BW) at a 72 MS/s sampling rate (Fs) with an oversampling ratio (OSR) of 7, and the power consumption is 2.4 mW. The (= SNDR + BW/Power) is 163.5 dB. The proposed structure in this study can achieve high resolution and wide BW with good power efficiency, without a filter calibration process, through the use of a ring amplifier in the PLNS-SAR ADC.


Author(s):  
Wen-Yaw Chung ◽  
Angelito A. Silverio ◽  
Roozbeh F. Ramezani ◽  
Jyun-Yu Lai ◽  
Angelina A. Silverio
Keyword(s):  
Sar Adc ◽  

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