Sampling-rate optimization of an interleaved-sampling front-end

2002 ◽  
Author(s):  
H.O. Johansson ◽  
M. Horowitz
Keyword(s):  
Sampling Rate ◽  
Front End ◽  
Rate Optimization

scholarly journals In Vivo Evaluation of a Subcutaneously Injectable Implant with a Low-Power Photoplethysmography ASIC for Animal Monitoring

Sensors ◽  
2020 ◽  
Vol 20 (24) ◽  
pp. 7335
Author(s):  
Jose Manuel Valero-Sarmiento ◽  
Parvez Ahmmed ◽  
Alper Bozkurt
Keyword(s):  
Software Defined Radio ◽  
Subcutaneous Tissue ◽  
Sampling Rate ◽  
Thick Layer ◽  
Total Power ◽  
Signal Acquisition ◽  
In Vivo Evaluation ◽  
Front End ◽  
Total Power Consumption

Photoplethysmography is an extensively-used, portable, and noninvasive technique for measuring vital parameters such as heart rate, respiration rate, and blood pressure. The deployment of this technology in veterinary medicine has been hindered by the challenges in effective transmission of light presented by the thick layer of skin and fur of the animal. We propose an injectable capsule system to circumvent these limitations by accessing the subcutaneous tissue to enable reliable signal acquisition even with lower light brightness. In addition to the reduction of power usage, the injection of the capsule offers a less invasive alternative to surgical implantation. Our current prototype combines two application-specific integrated circuits (ASICs) with a microcontroller and interfaces with a commercial light emitting diode (LED) and photodetector pair. These ASICs implement a signal-conditioning analog front end circuit and a frequency-shift keying (FSK) transmitter respectively. The small footprint of the ASICs is the key in the integration of the complete system inside a 40-mm long glass tube with an inner diameter of 4 mm, which enables its injection using a custom syringe similar to the ones used with microchip implants for animal identification. The recorded data is transferred wirelessly to a computer for post-processing by means of the integrated FSK transmitter and a software-defined radio. Our optimized LED duty cycle of 0.4% at a sampling rate of 200 Hz minimizes the contribution of the LED driver (only 0.8 mW including the front-end circuitry) to the total power consumption of the system. This will allow longer recording periods between the charging cycles of the batteries, which is critical given the very limited space inside the capsule. In this work, we demonstrate the wireless operation of the injectable system with a human subject holding the sensor between the fingers and the in vivo functionality of the subcutaneous sensing on a pilot study performed on anesthetized rat subjects.

scholarly journals Sampling Rate Optimization for Improving the Cascaded Integrator Comb Filter Characteristics

2021 ◽  
Vol 38 (1) ◽  
pp. 97-103
Author(s):  
Raouf Amrane ◽  
Youcef Brik ◽  
Samir Zeghlache ◽  
Mohamed Ladjal ◽  
Djamel Chicouche
Keyword(s):  
Signal Processing ◽  
Finite Impulse Response ◽  
Sampling Rate ◽  
Comb Filter ◽  
Existing Structures ◽  
High Sampling Rate ◽  
Cic Filter ◽  
Stopband Attenuation ◽  
Rate Optimization ◽  
Passband Droop

The cascaded integrator comb (CIC) filters are characterized by coefficient less and reduced hardware requirement, which make them an economical finite impulse response (FIR) class in many signal processing applications. They consist of an integrator section working at the high sampling rate and a comb section working at the low sampling rate. However, they don’t have well defined frequency response. To remedy this problem, several structures have been proposed but the performance is still unsatisfactory. Thence, this paper deals with the improvement of the CIC filter characteristics by optimizing its sampling rate. This solution increases the performance characteristics of CIC filters by improving the stopband attenuation and ripple as well as the passband droop. Also, this paper presents a comparison of the proposed method with some other existing structures such as the conventional CIC, the sharpened CIC, and the modified sharpened CIC filters, which has proven the effectiveness of the proposed method.

scholarly journals Design and Simulation of a Fully Digitized GNSS Receiver Front-End

2011 ◽  
Vol 2011 ◽  
pp. 1-11
Author(s):  
Yuan Yu ◽  
Qing Chang ◽  
Yuan Chen
Keyword(s):  
Sampling Rate ◽  
Sampling Technique ◽  
Navigation Systems ◽  
Front End ◽  
Optimal Value ◽  
Gnss Receivers ◽  
Rate Selection ◽  
Near Future ◽  
Global Navigation Systems ◽  
Rf Sampling

In the near future, RF front-ends of GNSS receivers may become very complicated when multifrequency signals are available from at least four global navigation systems. Based on the direct RF sampling technique, fully digitized receiver front-ends may solve the problem. In this paper, a direct digitization RF front-end scheme is presented. At first, a simplified sampling rate selection method is adopted to determine the optimal value. Then, the entire spectrum of GNSS signal is directly digitized through RF sampling at a very fast sampling rate. After that, the decimation and filtering network is designed to lower the sampling rate efficiently. It also realizes the digital downconversion of the signal of interest and the separation of narrow band signals from different navigation systems. The scheme can be flexibly implemented in software. Its effectiveness is proved through the experiment using simulated and true signals.

A 16 Bit 250MSPS Pipeline ADC

2014 ◽  
Vol 602-605 ◽  
pp. 2744-2747
Author(s):  
Ting Li ◽  
Yong Zhang ◽  
Yan Wang ◽  
Lu Liu ◽  
Xu Wang
Keyword(s):  
High Speed ◽  
Sampling Rate ◽  
Cmos Process ◽  
Pipelined Adc ◽  
Pipeline Adc ◽  
Front End ◽  
Sampling Network ◽  
Sinusoidal Input ◽  
High Efficient ◽  
Circuit Structure

In this paper, a 16 bit 250MSPS pipelined ADC is presented. To alleviate noise induced by mismatching of the MDAC sampling network and comparator sampling network, scaling network structure is applied; to implement high-speed sampling, a high-efficient front-end circuit structure is presented; to further improve the sampling rate, a double duty cycle clock circuit is presented; to improve the linearity of the ADC, the sample and hold circuit is removed and the improved clock controlled boost circuit is used. Simulation confirms that the ADC shows more than 95dB of SFDR for a 25.39-MHz sinusoidal input at 2Vpp at full sampling rate from a 0.18um CMOS process.

Sign in / Sign up

Export Citation Format

Share Document