Degradation Behavior and Mechanisms of E-mode GaN HEMTs with p-GaN Gate under High Temperature Gate Bias Stress

2021 ◽  
Author(s):  
WenYang Chen ◽  
Y.Q. Chen ◽  
KuiWei Geng
Keyword(s):  
High Temperature ◽  
Gate Bias ◽  
Degradation Behavior ◽  
Bias Stress ◽  
Gan Hemts ◽  
Gate Bias Stress

Investigating the degradation behavior caused by charge trapping effect under DC and AC gate-bias stress for InGaZnO thin film transistor

2011 ◽  
Vol 99 (2) ◽  
pp. 022104 ◽  
Author(s):  
Te-Chih Chen ◽  
Ting-Chang Chang ◽  
Tien-Yu Hsieh ◽  
Wei-Siang Lu ◽  
Fu-Yen Jian ◽  
...  
Keyword(s):  
Thin Film ◽  
Thin Film Transistor ◽  
Charge Trapping ◽  
Gate Bias ◽  
Degradation Behavior ◽  
Bias Stress ◽  
Trapping Effect ◽  
Gate Bias Stress

Degradation behavior and degradation mechanism of bridged-grain polycrystalline silicon thin film transistors under AC gate bias stress

2017 ◽  
Vol 32 (2) ◽  
pp. 91-96
Author(s):  
张猛 ZHANG Meng ◽  
夏之荷 XIA Zhi-he ◽  
周玮 ZHOU Wei ◽  
陈荣盛 CHEN Rong-sheng ◽  
王文 WONG Man ◽  
...  
Keyword(s):  
Thin Film ◽  
Thin Film Transistors ◽  
Polycrystalline Silicon ◽  
Degradation Mechanism ◽  
Gate Bias ◽  
Degradation Behavior ◽  
Silicon Thin Film ◽  
Bias Stress ◽  
Gate Bias Stress

Effect of Phosphorus Doped Poly Annealing on Threshold Voltage Stability and Thermal Oxide Reliability in 4H-SiC MOSFET

2020 ◽  
Vol 1004 ◽  
pp. 554-558
Author(s):  
Kwangwon Lee ◽  
Young Ho Seo ◽  
Taeseop Lee ◽  
Kyeong Seok Park ◽  
Martin Domeij ◽  
...  
Keyword(s):  
High Temperature ◽  
Threshold Voltage ◽  
Gate Oxide ◽  
Gate Bias ◽  
Annealed Condition ◽  
Threshold Voltage Shift ◽  
Bias Stress ◽  
Phosphorus Doped ◽  
Gate Bias Stress ◽  
Gate Oxide Integrity

We have investigated the effect of high temperature annealing of phosphorus doped poly on gate oxide integrity and device reliability. In NMOS capacitance analysis, unstable flat band voltage characteristics and lower oxide breakdown electric field were observed in wafers which received high temperature poly annealing at 1100 °C. Gate oxide integrity (GOI/Vramp) tests and time dependent dielectric breakdown (TDDB) tests were performed to evaluate wafer level reliability. Degraded GOI characteristics and poor gate oxide lifetime were obtained for the high temperature poly annealed condition. To evaluate package level reliability, high temperature gate bias (HTGB) stress tests were conducted. Some samples failed in positive gate bias stress and more severe negative threshold voltage shift was observed in negative gate bias stress for the high temperature poly annealed condition.

The Abnormal Degradation Behavior of ZnO TFT Under Gate Bias Stress

2019 ◽  
Vol 3 (8) ◽  
pp. 301-305 ◽  
Author(s):  
Chi-Sun Hwang ◽  
Sang Hee Ko Park ◽  
Sung Mook Chung ◽  
Jeong-Ik Lee ◽  
Yong Suk Yang ◽  
...  
Keyword(s):  
Gate Bias ◽  
Degradation Behavior ◽  
Bias Stress ◽  
Gate Bias Stress

The Effect of Forward Gate Bias Stress on the Noise Performance of Mesa Isolated GaN HEMTs

2015 ◽  
Vol 15 (1) ◽  
pp. 40-46 ◽  
Author(s):  
Olle Axelsson ◽  
Mattias Thorsell ◽  
Kristoffer Andersson ◽  
Niklas Rorsman
Keyword(s):  
Gate Bias ◽  
Noise Performance ◽  
Bias Stress ◽  
Gan Hemts ◽  
Gate Bias Stress

Two-step Electrical Degradation Behavior in α-InGaZnO Thin-film Transistor Under Gate-bias Stress

2013 ◽  
Vol 34 (5) ◽  
pp. 635-637 ◽  
Author(s):  
Fa-Hsyang Chen ◽  
Tung-Ming Pan ◽  
Ching-Hung Chen ◽  
Jiang-Hung Liu ◽  
Wu-Hsiung Lin ◽  
...  
Keyword(s):  
Thin Film ◽  
Thin Film Transistor ◽  
Gate Bias ◽  
Degradation Behavior ◽  
Bias Stress ◽  
Electrical Degradation ◽  
Gate Bias Stress
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