Effect of Phosphorus Doped Poly Annealing on Threshold Voltage Stability and Thermal Oxide Reliability in 4H-SiC MOSFET

2020 ◽  
Vol 1004 ◽  
pp. 554-558
Author(s):  
Kwangwon Lee ◽  
Young Ho Seo ◽  
Taeseop Lee ◽  
Kyeong Seok Park ◽  
Martin Domeij ◽  
...  
Keyword(s):  
High Temperature ◽  
Threshold Voltage ◽  
Gate Oxide ◽  
Gate Bias ◽  
Annealed Condition ◽  
Threshold Voltage Shift ◽  
Bias Stress ◽  
Phosphorus Doped ◽  
Gate Bias Stress ◽  
Gate Oxide Integrity

We have investigated the effect of high temperature annealing of phosphorus doped poly on gate oxide integrity and device reliability. In NMOS capacitance analysis, unstable flat band voltage characteristics and lower oxide breakdown electric field were observed in wafers which received high temperature poly annealing at 1100 °C. Gate oxide integrity (GOI/Vramp) tests and time dependent dielectric breakdown (TDDB) tests were performed to evaluate wafer level reliability. Degraded GOI characteristics and poor gate oxide lifetime were obtained for the high temperature poly annealed condition. To evaluate package level reliability, high temperature gate bias (HTGB) stress tests were conducted. Some samples failed in positive gate bias stress and more severe negative threshold voltage shift was observed in negative gate bias stress for the high temperature poly annealed condition.

1200 V SiC MOSFETs with Stable VTH under High Temperature Gate Bias Stress

2019 ◽  
Vol 963 ◽  
pp. 753-756
Author(s):  
Jimmy Franchi ◽  
Martin Domeij ◽  
Kwang Won Lee
Keyword(s):  
High Temperature ◽  
Threshold Voltage ◽  
High Field ◽  
Gate Oxide ◽  
Gate Bias ◽  
Bias Stress ◽  
Commercial Grade ◽  
Voltage Drift ◽  
Gate Bias Stress

In this work, threshold voltage drift of SiC MOSFET devices have been investigated. The drift during positive gate bias application was found to be moderate for three commercial grade devices, while the results for negative gate bias application differ widely. We demonstrate ON Semiconductor SiC MOSFETs with threshold voltage stability under both positive and negative bias stress due to an improved gate oxide process, and the influence of high field stress on the threshold voltage is additionally discussed. A long term transient high temperature gate bias stress is shown to cause a slight positive shift in the threshold voltage of the ON Semiconductor devices, while the on resistance remains constant.

DC and AC Gate-Bias Stability of Nanocrystalline Silicon Thin-Film Transistors Made on Colorless Polyimide Foil Substrates

2011 ◽  
Vol 1321 ◽  
Author(s):  
I-Chung Chiu ◽  
I-Chun Cheng ◽  
Jian Z. Chen ◽  
Jung-Jie Huang ◽  
Yung-Pei Chen
Keyword(s):  
Thin Film ◽  
Threshold Voltage ◽  
Thin Film Transistors ◽  
Nanocrystalline Silicon ◽  
Gate Bias ◽  
Threshold Voltage Shift ◽  
Voltage Shift ◽  
Bias Stress ◽  
Mechanical Tensile ◽  
Gate Bias Stress

ABSTRACTStaggered bottom-gate hydrogenated nanocrystalline silicon (nc-Si:H) thin-film transistors (TFTs) were demonstrated on flexible colorless polyimide substrates. The dc and ac bias-stress stability of these TFTs were investigated with and without mechanical tensile stress applied in parallel to the current flow direction. The findings indicate that the threshold voltage shift caused by an ac gate-bias stress was smaller compared to that caused by a dc gate-bias stress. Frequency dependence of threshold voltage shift was pronounced in the negative gate-bias stress experiments. Compared to TFTs under pure electrical gate-bias stressing, the stability of the nc-Si:H TFTs degrades further when the mechanical tensile strain is applied together with an electrical gate-bias stress.

Accurate evaluation of fast threshold voltage shift for SiC MOS devices under various gate bias stress conditions

2018 ◽  
Vol 57 (4S) ◽  
pp. 04FA07 ◽  
Author(s):  
Mitsuru Sometani ◽  
Mitsuo Okamoto ◽  
Tetsuo Hatakeyama ◽  
Yohei Iwahashi ◽  
Mariko Hayashi ◽  
...  
Keyword(s):  
Threshold Voltage ◽  
Stress Conditions ◽  
Gate Bias ◽  
Threshold Voltage Shift ◽  
Voltage Shift ◽  
Accurate Evaluation ◽  
Bias Stress ◽  
Mos Devices ◽  
Gate Bias Stress

scholarly journals Bias Stress Effects in Low Temperature Amorphous Hf-In-ZnO TFTs Using RF-sputtering HfO2 as High-k Gate Dielectric

2017 ◽  
Vol 12 (1) ◽  
pp. 18-23
Author(s):  
C. A. Pons-Flores ◽  
I. Hernández ◽  
I. Garduno ◽  
I. Mejía ◽  
M. Estrada
Keyword(s):  
Threshold Voltage ◽  
Gate Dielectric ◽  
Rf Sputtering ◽  
Electrical Performance ◽  
Gate Bias ◽  
Transistor Channel ◽  
Threshold Voltage Shift ◽  
Bias Stress ◽  
High K ◽  
Gate Bias Stress

In this work we analyze the electrical performance, contact resistance and the effects of positive and negative gatebias stress of Hf-In-ZnO/HfO2 thin film transistors. Devices were fabricated using RF-magnetron sputtering at room temperature and fully patterned, with operation voltage below 6 V. Devices with drain-currents up to 2x10-6 A and threshold voltages of ~2 V were analyzed under negative and positive gate bias stress. Devices under negative gate-bias stress showed a slightly threshold voltage shift due to the transistor channel is depleted of electrons at the channel/dielectric interface. Devices under positive gate-bias stress, showed threshold voltage shifts in the negative direction due to the reversible charge/discharge effect of the electrons in pre-existing high-k HfO2 bulk traps. Positive gate-bias stress does not cause any degeneration, since stressed devices tend to recover after 5 mins.

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