Optimization for the growth condition of In-situ SiNx cap layer on ultrathin barrier InAlGaN/GaN heterostructures by Metal-Organic Chemical Vapor Deposition

We investigate the dependence of material and electrical properties on the growth temperature of In-situ SiNx on InAlGaN/GaN heterostructures grown by Metal-Organic Chemical Vapor Deposition. Degradation of the interface between SiNx and InAlGaN layer was observed when growth temperature is below 900 ℃ or above 1100 ℃. With the optimized SiNx growth temperature, the high-quality SiNx and low interface trap density can be realized. Thus, the double-sweep capacitance-voltage measurement showed a sharp transition from charge accumulation to depletion with low hysteresis of 0.09 V. A small threshold-voltage shift after gate bias stress (1001 s) was also characterized by I-V measurement.

Mechanical Stress Stability of Flexible Amorphous Zinc Tin Oxide Thin-Film Transistors

Due to their low-temperature processing capability and ionic bonding configuration, amorphous oxide semiconductors (AOS) are well suited for applications within future mechanically flexible electronics. Over the past couple of years, amorphous zinc tin oxide (ZTO) has been proposed as indium and gallium-free and thus more sustainable alternative to the widely deployed indium gallium zinc oxide (IGZO). The present study specifically focuses on the strain-dependence of elastic and electrical properties of amorphous zinc tin oxide thin-films sputtered at room temperature. Corresponding MESFETs have been compared regarding their operation stability under mechanical bending for radii ranging from 5 to 2 mm. Force-spectroscopic measurements yield a plastic deformation of ZTO as soon as the bending-induced strain exceeds 0.83 %. However, the electrical properties of ZTO determined by Hall effect measurements at room temperature are demonstrated to be unaffected by residual compressive and tensile strain up to 1.24 %. Even for the maximum investigated tensile strain of 1.26 %, the MESFETs exhibit a reasonably consistent performance in terms of current on/off ratios between six and seven orders of magnitude, a subthreshold swing around 350 mV/dec and a field-effect mobility as high as 7.5 cm2V−1s−1. Upon gradually subjecting the transistors to higher tensile strain, the channel conductivity steadily improves and consequently, the field-effect mobility increases by nearly 80 % while bending the devices around a radius of 2 mm. Further, a reversible threshold voltage shift of about −150 mV with increasing strain is observable. Overall, amorphous ZTO provides reasonably stable electrical properties and device performance for bending-induced tensile strain up to at least 1.26 % and thus represent a promising material of choice considering novel bendable and transparent electronics.

Three-Dimensional TID Hardening Design for 14 nm Node SOI FinFETs

The fin field-effect transistor (FinFET) has been the mainstream technology on the VLSI platform since the 22 nm node. The silicon-on-insulator (SOI) FinFET, featuring low power consumption, superior computational power and high single-event effect (SEE) resistance, shows advantages in integrated circuits for space applications. In this work, a rad-hard design methodology for SOI FinFETs is shown to improve the devices’ tolerance against the Total Ionizing Dose (TID) effect. Since the fin height direction enables a new dimension for design optimization, a 3D Source/Drain (S/D) design combined with a gate dielectric de-footing technique, which has been readily developed for the 14 nm node FinFETs, is proposed as an effective method for SOI FinFETs’ TID hardening. More importantly, the governing mechanism is thoroughly investigated using fully calibrated technology computer-aided design (TCAD) simulations to guide design optimizations. The analysis demonstrates that the 3D rad-hard design can modulate the leakage path in 14 nm node n-type SOI FinFETs, effectively suppress the transistors’ sensitivity to the TID charge and reduce the threshold voltage shift by >2×. Furthermore, the rad-hard design can reduce the electric field in the BOX region and lower its charge capture rate under radiation, further improving the transistor’s robustness.

The Combined Effects of Cycling Endurance and TID on Floating Gate Memory Cells

In this paper, the combined effects of cycling endurance and radiation on floating gate memory cell are investigated in detail, the results indicate that: 1.The programmed flash cells with a prior appropriate number of program and erase cycling stress exhibit much smaller threshold voltage shift than their counterpart in response to radiation, which is mainly ascribed to the recombination of trapped electrons (introduced by cycling stress) and trapped holes (introduced by irradiation) in the oxide surrounding the floating gate; 2.The radiation induced transconductance degradation in prior cycled flash cell is more severe than those without cycling stress in both of the programmed state and erased state; 3. Radiation is more likely to induce interface generation in programmed state than in erased state. This paper will be useful in understanding the issues involved in cycling endurance and radiation effects as well as in designing radiation hardened floating gate memory cells.

Numerical Analysis of Oxygen-Related Defects in Amorphous In-W-O Nanosheet Thin-Film Transistor

The integration of 4 nm thick amorphous indium tungsten oxide (a-IWO) and a hafnium oxide (HfO2) high-κ gate dielectric has been demonstrated previously as one of promising amorphous oxide semiconductor (AOS) thin-film transistors (TFTs). In this study, the more positive threshold voltage shift (∆VTH) and reduced ION were observed when increasing the oxygen ratio during a-IWO deposition. Through simple material measurements and Technology Computer Aided Design (TCAD) analysis, the distinct correlation between different chemical species and the corresponding bulk and interface density of states (DOS) parameters were systematically deduced, validating the proposed physical mechanisms with a quantum model for a-IWO nanosheet TFT. The effects of oxygen flow on oxygen interstitial (Oi) defects were numerically proved for modulating bulk dopant concentration Nd and interface density of Gaussian acceptor trap NGA at the front channel, significantly dominating the transfer characteristics of a-IWO TFT. Furthermore, based on the studies of density functional theory (DFT) for the correlation between formation energy Ef of Oi defect and Fermi level (EF) position, we propose a numerical methodology for monitoring the possible concentration distribution of Oi as a function of a bias condition for AOS TFTs.

Physical and Electrical Analysis of Poly-Si Channel Effect on SONOS Flash Memory

In this study, polycrystalline silicon (poly-Si) is applied to silicon-oxide-nitride-oxide-silicon (SONOS) flash memory as a channel material and the physical and electrical characteristics are analyzed. The results show that the surface roughness of silicon nitride as charge trapping layer (CTL) is enlarged with the number of interface traps and the data retention properties are deteriorated in the device with underlying poly-Si channel which can be serious problem in gate-last 3D NAND flash memory architecture. To improve the memory performance, high pressure deuterium (D2) annealing is suggested as a low-temperature process and the program window and threshold voltage shift in data retention mode is compared before and after the D2 annealing. The suggested curing is found to be effective in improving the device reliability.

Theoretical and Experimental Substractions of Device Temperature Determination Utilizing I-V Characterization Applied on AlGaN/GaN HEMT

A differential analysis of electrical attributes, including the temperature profile and trapping phenomena is introduced using a device analytical spatial electrical model. The resultant current difference caused by the applied voltage variation is divided into isothermal and thermal sections, corresponding to the instantaneous time- or temperature-dependent change. The average temperature relevance is explained in the theoretical section with respect to the thermal profile and major parameters of the device at the operating point. An ambient temperature variation method has been used to determine device average temperature under quasi-static state and pulse operation, was compared with respect to the threshold voltage shift of a high-electron-mobility transistor (HEMT). The experimental sections presents theoretical subtractions of average channel temperature determination including trapping phenomena adapted for the AlGaN/GaN HEMT. The theoretical results found using the analytical model, allow for the consolidation of specific methodologies for further research to determine the device temperature based on spatially distributed and averaged parameters.

Effects of polyimide curing on image sticking behaviors of flexible displays

Flexible displays on a polyimide (PI) substrate are widely regarded as a promising next-generation display technology due to their versatility in various applications. Among other bendable materials used as display panel substrates, PI is especially suitable for flexible displays for its high glass transition temperature and low coefficient of thermal expansion. PI cured under various temperatures (260 °C, 360 °C, and 460 °C) was implemented in metal–insulator–metal (MIM) capacitors, amorphous indium gallium zinc oxide (a-IGZO) thin-film transistors (TFT), and actual display panels to analyze device stability and panel product characteristics. Through electrical analysis of the MIM capacitor, it was confirmed that the charging effect in the PI substrates intensified as the PI curing temperature increased. The threshold voltage shift (ΔVth) of the samples was found to increase with rising curing temperature under negative bias temperature stress (NBTS) due to the charging effect. Our analyses also show that increasing ΔVth exacerbates the image sticking phenomenon observed in display panels. These findings ultimately present a direct correlation between the curing temperature of polyimide substrates and the panel image sticking phenomenon, which could provide an insight into the improvement of future PI-substrate-based displays.