Effect of Phosphorus Doped Poly Annealing on Threshold Voltage Stability and Thermal Oxide Reliability in 4H-SiC MOSFET

We have investigated the effect of high temperature annealing of phosphorus doped poly on gate oxide integrity and device reliability. In NMOS capacitance analysis, unstable flat band voltage characteristics and lower oxide breakdown electric field were observed in wafers which received high temperature poly annealing at 1100 °C. Gate oxide integrity (GOI/Vramp) tests and time dependent dielectric breakdown (TDDB) tests were performed to evaluate wafer level reliability. Degraded GOI characteristics and poor gate oxide lifetime were obtained for the high temperature poly annealed condition. To evaluate package level reliability, high temperature gate bias (HTGB) stress tests were conducted. Some samples failed in positive gate bias stress and more severe negative threshold voltage shift was observed in negative gate bias stress for the high temperature poly annealed condition.

Silicon Surface Passivation in HF Solutions for Improved Gate Oxide Reliability

The silicon surface passivation with diluted HF solutions is hereby explained. Without a very stable, correct Si-H surface passivation, a rough silicon surface can be obtained, leading to poor gate oxide integrity or bad epi film quality. Detailed mechanism are depicted and solutions to obtain best Si-H passivated surface are given

Investigation of Wet Clean Induced Dielectric Surface Static Charge and its Impact on Gate Oxide Integrity

The static electricity of wet clean was characterized by contactless surface voltage measurement on silicon oxide dielectric in this study. The paper shows surface static charge at wafer center caused by a single wafer spin cleaning tool. Deionized water (DIW) rinse was verified as the critical step of inducing static charge. It was demonstrated by metal oxide semiconductor (MOS) capacitor that such serious dielectric static charge would degrade gate oxide integrity (GOI). With dissolved CO2to lower DIW resistance, surface static charge at wafer center is reduced and degraded GOI is restored as a result.