Sparsity-aware Power Gating for Tensor Cores

2021 ◽  
Author(s):  
Ehsan Atoofian
Keyword(s):  
Power Gating

Energy Minimum Operation with Self Synchronous Gate-Level Autonomous Power Gating and Voltage Scaling

2012 ◽  
Vol E95-C (4) ◽  
pp. 546-554 ◽  
Author(s):  
Benjamin DEVLIN ◽  
Makoto IKEDA ◽  
Kunihiro ASADA
Keyword(s):  
Voltage Scaling ◽  
Power Gating ◽  
Energy Minimum

Magnetic nonvolatile flip-flops with spin-Hall assistance for power gating in ternary systems

2020 ◽  
Vol 19 (3) ◽  
pp. 1175-1186
Author(s):  
Ali Asghar Javadi ◽  
Mehrdad Morsali ◽  
Mohammad Hossein Moaiyeri
Keyword(s):  
Ternary Systems ◽  
Power Gating

An integrated DFT solution for power reduction in scan test applications by low power gating scan cell

Integration ◽  
2017 ◽  
Vol 57 ◽  
pp. 108-124 ◽  
Author(s):  
Mahshid Mojtabavi Naeini ◽  
Sreedharan Baskara Dass ◽  
Chia Yee Ooi ◽  
Tomokazu Yoneda ◽  
Michiko Inoue
Keyword(s):  
Low Power ◽  
Power Reduction ◽  
Power Gating ◽  
Scan Test

Probabilistic Analysis of Power-Gating in Network-on-Chip Routers

2019 ◽  
Vol 66 (2) ◽  
pp. 242-246 ◽  
Author(s):  
Nasim Nasirian ◽  
Reza Soosahabi ◽  
Magdy A. Bayoumi
Keyword(s):  
Probabilistic Analysis ◽  
Network On Chip ◽  
Power Gating ◽  
On Chip

scholarly journals Carry select adder with sub-block power gating for reducing active-mode leakage in sub-32-nm VLSIs

2011 ◽  
Vol 8 (16) ◽  
pp. 1322-1329
Author(s):  
Huan Minh Vo ◽  
Chul-Moon Jung ◽  
Eun-Sub Lee ◽  
Kyeong-Sik Min
Keyword(s):  
Power Gating ◽  
Active Mode ◽  
Carry Select Adder
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