Current-Loop Bandwidth Extension for PMSM Servo System Based on SiC Inverter and FPGA

2021 ◽  
Author(s):  
Qiwei Xie ◽  
Jianqi Qiu
Keyword(s):  
Servo System ◽  
Current Loop ◽  
Bandwidth Extension ◽  
Loop Bandwidth

Shipboard Radar Servo System PID Parameters Turning Based on Simulink

2014 ◽  
Vol 536-537 ◽  
pp. 1121-1124
Author(s):  
Qiu Qi Ding ◽  
Min Tao ◽  
Xin Rong Wang
Keyword(s):  
Pid Control ◽  
Dynamic Performance ◽  
Servo System ◽  
Mathematic Model ◽  
Parameter Tuning ◽  
Fuzzy Pid Control ◽  
Simulation Experiments ◽  
Loop Bandwidth ◽  
Self Tuning ◽  
On Line

This paper expounds the structure and principle of shipboard radar servo system, according to traditional PID parameter tuning problem, the parameter self-tuning fuzzy PID control technology is applied to the servo system position loop, through the simulation experiments show that the method can 't depend on the mathematic model of the system, and according to the relation between input and output of the PID parameters on-line adjustment, automatic adjustment loop bandwidth, increase the system dynamic performance and steady performance, strong robustness and adaptability.

A NOVEL FRACTIONAL-N PLL BASED ON A SIMPLE REFERENCE MULTIPLIER

2012 ◽  
Vol 21 (06) ◽  
pp. 1240010 ◽  
Author(s):  
XIAO PU ◽  
KRISHNASWAMY NAGARAJ ◽  
JACOB ABRAHAM ◽  
AXEL THOMSEN
Keyword(s):  
Frequency Synthesizer ◽  
Quantization Error ◽  
Quantization Noise ◽  
Successful Implementation ◽  
Noise Shaping ◽  
Bandwidth Extension ◽  
Loop Bandwidth ◽  
Update Rate ◽  
Oversampling Ratio

A wide loop bandwidth in fractional-N PLL is desirable for good jitter performance. However, a wider bandwidth reduces the effective oversampling ratio between update rate and loop bandwidth, making quantization error a much bigger noise contributor. A successful implementation of a wideband frequency synthesizer is in managing jitter and spurious performance. In this paper we present a new PLL architecture for bandwidth extension. By using clock squaring buffers with built-in offsets, multiple clock edges are extracted from a single reference cycle and utilized for phase update, thereby effectively forming a reference multiplier. This enables a higher oversampling ratio for better quantization noise shaping and makes a wideband fractional-N PLL possible.

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