Run-time communication bypassing for energy-efficient, low-latency per-core DVFS on Network-on-Chip

Network on Chip(NoC)，a new proposed solution to solve global communication problem in complex System on Chip (SoC) design，has absorbed more and more researchers to do research in this area. Due to some distinct characteristics, NoC is different from both traditional off-chip network and traditional on-chip bus，and is facing with the huge design challenge. NoC router design is one of the most important issues in NoC system. The paper present a high-performance, low-latency two-stage pipelined router architecture suitable for NoC designs and providing a solution to irregular 2Dmesh topology for NoC. The key features of the proposed Mix Router are its suitability for 2Dmesh NoC topology and its capability of suorting both full-adaptive routing and deterministic routing algorithm.

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Energy-Efficient Networks-on-Chip Architectures: Design and Run-Time Optimization

Network-on-Chip Security and Privacy ◽

10.1007/978-3-030-69131-8_3 ◽

2021 ◽

pp. 55-75

Author(s):

Sumit K. Mandal ◽

Anish Krishnakumar ◽

Umit Y. Ogras

Keyword(s):

Energy Efficient ◽

Networks On Chip ◽

Time Optimization ◽

Run Time ◽

On Chip

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Dual Monitoring Communication for Self-Aware Network-on-Chip

International Journal of Adaptive Resilient and Autonomic Systems ◽

10.4018/jaras.2012070105 ◽

2012 ◽

Vol 3 (3) ◽

pp. 72-91

Author(s):

Liang Guang ◽

Ethiopia Nigussie ◽

Juha Plosila ◽

Hannu Tenhunen

Keyword(s):

High Speed ◽

Data Communication ◽

Cmos Technology ◽

Network On Chip ◽

Time Profile ◽

Self Awareness ◽

Monitoring Networks ◽

Communication Architecture ◽

Run Time ◽

On Chip

Self-aware and adaptive Network-on-Chip (NoC) with dual monitoring networks is presented. Proper monitoring interface is an essential prerequisite to adaptive system reconfiguration in parallel on-chip computing. This work proposes a DMC (dual monitoring communication) architecture to support self-awareness on the NoC platform. One type of monitoring communication is integrated with data channel, in order to trace the run-time profile of data communication in high-speed on-chip networking. The other type is separate from the data communication, and is needed to report the run-time profile to the supervising monitor. Direct latency monitoring on mesochronous NoC is presented as a case study and is directly traced in the integrated communication with a novel latency monitoring table in each router. The latency information is reported by the separate monitoring communication to the supervising monitor, which reconfigures the system to adjust the latency, for instance by dynamic voltage and frequency scaling. With quantitative evaluation using synthetic traces and real applications, the effectiveness and efficiency of direct latency monitoring with DMC architecture is demonstrated. The area overhead of DMC architecture is estimated to be small in 65nm CMOS technology.

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