Dual Monitoring Communication for Self-Aware Network-on-Chip

2012 ◽  
Vol 3 (3) ◽  
pp. 72-91
Author(s):  
Liang Guang ◽  
Ethiopia Nigussie ◽  
Juha Plosila ◽  
Hannu Tenhunen
Keyword(s):  
High Speed ◽  
Data Communication ◽  
Cmos Technology ◽  
Network On Chip ◽  
Time Profile ◽  
Self Awareness ◽  
Monitoring Networks ◽  
Communication Architecture ◽  
Run Time ◽  
On Chip

Self-aware and adaptive Network-on-Chip (NoC) with dual monitoring networks is presented. Proper monitoring interface is an essential prerequisite to adaptive system reconfiguration in parallel on-chip computing. This work proposes a DMC (dual monitoring communication) architecture to support self-awareness on the NoC platform. One type of monitoring communication is integrated with data channel, in order to trace the run-time profile of data communication in high-speed on-chip networking. The other type is separate from the data communication, and is needed to report the run-time profile to the supervising monitor. Direct latency monitoring on mesochronous NoC is presented as a case study and is directly traced in the integrated communication with a novel latency monitoring table in each router. The latency information is reported by the separate monitoring communication to the supervising monitor, which reconfigures the system to adjust the latency, for instance by dynamic voltage and frequency scaling. With quantitative evaluation using synthetic traces and real applications, the effectiveness and efficiency of direct latency monitoring with DMC architecture is demonstrated. The area overhead of DMC architecture is estimated to be small in 65nm CMOS technology.

scholarly journals Adaptivity Support for MPSoCs Based on Process Migration in Polyhedral Process Networks

VLSI Design ◽  
2012 ◽  
Vol 2012 ◽  
pp. 1-17 ◽  
Author(s):  
Emanuele Cannella ◽  
Onur Derin ◽  
Paolo Meloni ◽  
Giuseppe Tuveri ◽  
Todor Stefanov
Keyword(s):  
Real Life ◽  
Data Communication ◽  
Network On Chip ◽  
Process Migration ◽  
Model Of Computation ◽  
Process Networks ◽  
Time Migration ◽  
Migration Mechanism ◽  
Run Time ◽  
On Chip

System adaptivity is becoming an important feature of modern embedded multiprocessor systems. To achieve the goal of system adaptivity when executing Polyhedral Process Networks (PPNs) on a generic tiled Network-on-Chip (NoC) MPSoC platform, we propose an approach to enable the run-time migration of processes among the available platform resources. In our approach, process migration is allowed by a middleware layer which comprises two main components. The first component concerns the inter-tile data communication between processes. We develop and evaluate a number of different communication approaches which implement the semantics of the PPN model of computation on a generic NoC platform. The presented communication approaches do not depend on the mapping of processes and have been implemented on a Network-on-Chip multiprocessor platform prototyped on an FPGA. Their comparison in terms of the introduced overhead is presented in two case studies with different communication characteristics. The second middleware component allows the actual run-time migration of PPN processes. To this end, we propose and evaluate a process migration mechanism which leverages the PPN model of computation to guarantee a predictable and efficient migration procedure. The efficiency and applicability of the proposed migration mechanism is shown in a real-life case study.

scholarly journals System-on-chip sensor fusion front-end self-healing design for network-on-chip digital communications

2017 ◽  
Author(s):  
Emmanuel Seaman ◽  
Jason Du
Keyword(s):  
Sensor Fusion ◽  
Data Storage ◽  
Communication Systems ◽  
High Speed ◽  
Process Variations ◽  
Cmos Technology ◽  
Network On Chip ◽  
Cmos Process ◽  
Self Healing ◽  
On Chip

With the ultra-scaling of CMOS technology, high-speed and low-power millimeter-wave communication systems for network-on-chip have been attracting more and more attentions due to the wider bandwidth and higher data rate that can meet the ever-increasing needs for multimedia, massive external data storage, or even biomedical applications. However, from manufacturing’s perspective, the circuits implementations are increasingly susceptible to fabrication process variations with the scaling of CMOS technology, which results in loss of yield rate. To solve this issue, a sensor-fusion solution is proposed in this paper by adding multiple on-chip sensors, including power detectors, temperature sensors, information envelope detectors and related filters, instrumentation amplifiers using a standard CMOS process. These sensors and detectors aim to collect critical system performance and environmental parameters, which will be utilized by a self-healing and optimization algorithm to adjust the state of system components by digitized control knobs.

scholarly journals Architectural Enhancement of Network on Chip

2019 ◽  
Vol 9 (1S3) ◽  
pp. 287-290
Keyword(s):  
Data Transmission ◽  
Architectural Design ◽  
Data Communication ◽  
Theoretical Data ◽  
Network On Chip ◽  
Communication Architecture ◽  
Serial Data ◽  
Design Suggestion ◽  
On Chip ◽  
Simultaneous Transmission

This paper gives a new architectural design suggestion of NoC, with efficient way of communication. Firstly, to create a serial data communication architecture in competence with the existing widely used parallel form of data transmission and reception [1]. Secondly to enable simultaneous transmission and reception between more than one module at the same time. Thirdly to create the architecture that is modifiable as per the need of user. The theoretical data rate calculated was 300 MBps. The throughput we achieved after the completion is 250MBps.

scholarly journals System-on-chip sensor fusion front-end self-healing design for network-on-chip digital communications

2017 ◽  
Author(s):  
Emmanuel Seaman ◽  
Jason Yuan Du
Keyword(s):  
Sensor Fusion ◽  
Data Storage ◽  
Communication Systems ◽  
High Speed ◽  
Process Variations ◽  
Cmos Technology ◽  
Network On Chip ◽  
Cmos Process ◽  
Self Healing ◽  
On Chip

With the ultra-scaling of CMOS technology, high-speed and low-power millimeter-wave communication systems for network-on-chip have been attracting more and more attentions due to the wider bandwidth and higher data rate that can meet the ever-increasing needs for multimedia, massive external data storage, or even biomedical applications. However, from manufacturing’s perspective, the circuits implementations are increasingly susceptible to fabrication process variations with the scaling of CMOS technology, which results in loss of yield rate. To solve this issue, a sensor-fusion solution is proposed in this paper by adding multiple on-chip sensors, including power detectors, temperature sensors, information envelope detectors and related filters, instrumentation amplifiers using a standard CMOS process. These sensors and detectors aim to collect critical system performance and environmental parameters, which will be utilized by a self-healing and optimization algorithm to adjust the state of system components by digitized control knobs.

scholarly journals System-on-chip sensor fusion front-end self-healing design for network-on-chip digital communications

2017 ◽  
Author(s):  
Emmanuel Seaman ◽  
Jason Yuan Du
Keyword(s):  
Sensor Fusion ◽  
Data Storage ◽  
Communication Systems ◽  
High Speed ◽  
Process Variations ◽  
Cmos Technology ◽  
Network On Chip ◽  
Cmos Process ◽  
Self Healing ◽  
On Chip

With the ultra-scaling of CMOS technology, high-speed and low-power millimeter-wave communication systems for network-on-chip have been attracting more and more attentions due to the wider bandwidth and higher data rate that can meet the ever-increasing needs for multimedia, massive external data storage, or even biomedical applications. However, from manufacturing’s perspective, the circuits implementations are increasingly susceptible to fabrication process variations with the scaling of CMOS technology, which results in loss of yield rate. To solve this issue, a sensor-fusion solution is proposed in this paper by adding multiple on-chip sensors, including power detectors, temperature sensors, information envelope detectors and related filters, instrumentation amplifiers using a standard CMOS process. These sensors and detectors aim to collect critical system performance and environmental parameters, which will be utilized by a self-healing and optimization algorithm to adjust the state of system components by digitized control knobs.

Network-on-Chip for Low Power MAP Decoder Using Folded Technique and CORDIC Algorithm for 5G Network

2021 ◽  
pp. 96-108
Author(s):  
Shiyamala S. ◽  
Vijay Soorya J. ◽  
Sanjay P. S. ◽  
Sathappan K.
Keyword(s):  
Turbo Codes ◽  
High Speed ◽  
Life Time ◽  
Full Adder ◽  
Network On Chip ◽  
Cordic Algorithm ◽  
Effective Manner ◽  
Constraint Length ◽  
On Chip ◽  
Map Decoder

With different constraint length (K), time scale, and code rate, modified MAP (maximum a posteriori) decoder architecture using folding technique, which has a linear life time chart, is developed, and dedicated turbo codes will be placed in a network-on-chip for various wireless applications. Folded techniques mitigated the number of latches used in interleaving and deinterleaving unit by adopting forward and backward resource utilizing method to M-2, where M is the number of rows and end-to-end delay get reduced to 2M. By replacing conventional full adder by high speed adder using 2 x 1 multiplexer to calculate the forward state metrics and reverse state metrics will minimize the power consumption utilization in an effective manner. In s similar way, CORDIC (Coordinated ROtation DIgital Computer) algorithm is used to calculate the LLR value and confer a highly precise value with less computational complexity by means of only shifting and adding methods.

scholarly journals Congestion-aware wireless network-on-chip for high-speed communication

Automatika ◽  
2019 ◽  
Vol 61 (1) ◽  
pp. 92-98
Author(s):  
M. Devanathan ◽  
V. Ranganathan ◽  
P. Sivakumar
Keyword(s):  
Wireless Network ◽  
High Speed ◽  
Network On Chip ◽  
On Chip ◽  
Congestion Aware

A LOW POWER AND VARIATION-INSENSITIVE CURRENT-MODE SIGNALING SCHEME

2013 ◽  
Vol 22 (08) ◽  
pp. 1350068
Author(s):  
XINSHENG WANG ◽  
YIZHE HU ◽  
LIANG HAN ◽  
JINGHU LI ◽  
CHENXU WANG ◽  
...  
Keyword(s):  
Low Power ◽  
High Speed ◽  
Current Mode ◽  
Signal Propagation ◽  
Cmos Technology ◽  
Propagation Delay ◽  
Noise Performance ◽  
On Chip ◽  
Variation Tolerance ◽  
Driving Signal

Process and supply variations all have a large influence on current-mode signaling (CMS) circuits, limiting their application on the fields of high-speed low power communication over long on-chip interconnects. A variation-insensitive CMS scheme (CMS-Bias) was offered, employing a particular bias circuit to compensate the effects of variations, and was robust enough against inter-die and intra-die variations. In this paper, we studied in detail the principle of variation tolerance of the CMS circuit and proposed a more suitable bias circuit for it. The CMS-Bias with the proposed bias circuit (CMS-Proposed) can acquire the same variation tolerance but consume less energy, compared with CMS-Bias with the original bias circuit (CMS-Original). Both the CMS schemes were fabricated in 180 nm CMOS technology. Simulation and measured results indicate that the two CMS interconnect circuits have the similar signal propagation delay when driving signal over a 10 mm line, but the CMS-Proposed offers about 9% reduction in energy/bit and 7.2% reduction in energy-delay-product (EDP) over the CMS-Original. Simulation results show that the two CMS schemes only change about 5% in delay when suffering intra-die variations, and have the same robustness against inter-die variations. Both simulation and measurements all show that the proposed bias circuits, employing self-biasing structure, contribute to robustness against supply variations to some extent. Jitter analysis presents the two CMS schemes have the same noise performance.

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