In this paper, a new methodology to compare the robustness of sensor structures employed in radiofrequency design for test (RF DFT) architectures for RF integrated circuits (ICs) is proposed. First, the yield loss and defect level of the test technique is evaluated using a statistical model of the Circuit under Test (obtained through non-parametric statistics and copula theory). Then, by carrying out the dispersion analysis of the sensor architecture, a figure of merit is established. This methodology reduces the number of iterations in the design flow of RF DFT sensors and makes it possible to evaluate process dispersion. The case study is a SiGe:C BiCMOS LNA tested by a single-probe measurement.
Design-for-Test of Mixed-Signal Integrated Circuits
