Advances in Testing and Design-for-Test Solutions for M3D Integrated Circuits

Author(s):  
Sanmitra Banerjee ◽  
Arjun Chaudhuri ◽  
Shao-Chun Hung ◽  
Krishnendu Chakrabarty
2012 ◽  
Vol 4 (5) ◽  
pp. 515-521 ◽  
Author(s):  
Conrado K. Mesadri ◽  
Aziz Doukkali ◽  
Philippe Descamps ◽  
Christophe Kelma

In this paper, a new methodology to compare the robustness of sensor structures employed in radiofrequency design for test (RF DFT) architectures for RF integrated circuits (ICs) is proposed. First, the yield loss and defect level of the test technique is evaluated using a statistical model of the Circuit under Test (obtained through non-parametric statistics and copula theory). Then, by carrying out the dispersion analysis of the sensor architecture, a figure of merit is established. This methodology reduces the number of iterations in the design flow of RF DFT sensors and makes it possible to evaluate process dispersion. The case study is a SiGe:C BiCMOS LNA tested by a single-probe measurement.


2013 ◽  
Vol 427-429 ◽  
pp. 636-639
Author(s):  
Guo Gang Liao ◽  
Jun Li

Nowadays with the increases of the density of large scale integrated circuits, researches of Design for Test (DFT) become more and more important, JTAG (JTAG: Joint Test Action Group, also called Boundary Scan ) has been widely used in test area , which improves the testability and reliability of mixed-signal circuits. This paper puts forward a scheme to design a Built-in Test System (BITS) based on boundary scan technology. The BITS is realized in a weapon electronic control system, which is composed of mixed-signal circuits including ARM, AD/DA, FPGA, etc. With this method, several test experiments are carried out in the BITS, which include infrastructure integrity test, interconnect test, cluster test, AD/DA test and so on. The results of experiments show that the Built-in Test System based on JTAG can work normally, which is able to reduce effectively the complexity and the time of test. In a word, the capability of BITS is viable and the system is a virtual tool in the process of DFT design and application.


Author(s):  
Simon Thomas

Trends in the technology development of very large scale integrated circuits (VLSI) have been in the direction of higher density of components with smaller dimensions. The scaling down of device dimensions has been not only laterally but also in depth. Such efforts in miniaturization bring with them new developments in materials and processing. Successful implementation of these efforts is, to a large extent, dependent on the proper understanding of the material properties, process technologies and reliability issues, through adequate analytical studies. The analytical instrumentation technology has, fortunately, kept pace with the basic requirements of devices with lateral dimensions in the micron/ submicron range and depths of the order of nonometers. Often, newer analytical techniques have emerged or the more conventional techniques have been adapted to meet the more stringent requirements. As such, a variety of analytical techniques are available today to aid an analyst in the efforts of VLSI process evaluation. Generally such analytical efforts are divided into the characterization of materials, evaluation of processing steps and the analysis of failures.


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