A new methodology for optimal RF DFT sensor design

In this paper, a new methodology to compare the robustness of sensor structures employed in radiofrequency design for test (RF DFT) architectures for RF integrated circuits (ICs) is proposed. First, the yield loss and defect level of the test technique is evaluated using a statistical model of the Circuit under Test (obtained through non-parametric statistics and copula theory). Then, by carrying out the dispersion analysis of the sensor architecture, a figure of merit is established. This methodology reduces the number of iterations in the design flow of RF DFT sensors and makes it possible to evaluate process dispersion. The case study is a SiGe:C BiCMOS LNA tested by a single-probe measurement.

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A Novel Design and Optimization Approach for Low Noise Amplifiers (LNA) Based on MOST Scattering Parameters and the gm/ID Ratio

Electronics ◽

10.3390/electronics9050785 ◽

2020 ◽

Vol 9 (5) ◽

pp. 785

Author(s):

Juan L. Castagnola ◽

Fortunato C. Dualibe ◽

Agustín M. Laprovitta ◽

Hugo García-Vázquez

Keyword(s):

Integrated Circuits ◽

Noise Figure ◽

Low Noise ◽

Low Noise Amplifiers ◽

Optimization Approach ◽

Scattering Parameters ◽

Rf Integrated Circuits ◽

Design And Optimization ◽

Noise Amplifier

This work presents a new design methodology for radio frequency (RF) integrated circuits based on a unified analysis of the scattering parameters of the circuit and the gm/ID ratio of the involved transistors. Since the scattering parameters of the circuits are parameterized by means of the physical characteristics of transistors, designers can optimize transistor size and biasing to comply with the circuit specifications given in terms of S-parameters. A complete design of a cascode low noise amplifier (LNA) in MOS 65 nm technology is taken as a case study in order to validate the approach. In addition, this methodology permits the identification of the best trade-off between the minimum noise figure and the maximum gain for the LNA in a very simple way.

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Advanced Laser Probe Techniques Applied to FA of RF Integrated Circuits - A Case Study

ISTFA 2012: Conference Proceedings from the 38th International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2012p0223 ◽

2012 ◽

Author(s):

Mark Kimball ◽

Christopher Nemirow

Keyword(s):

Integrated Circuits ◽

Measurement Technique ◽

Capacitive Coupling ◽

Challenging Problem ◽

Rf Integrated Circuits ◽

Laser Probe ◽

Voltage Imaging ◽

Alternative Measurement ◽

Capacitive Loading

Abstract Failure analysis of RFIC’s can be a challenging problem, particularly as frequencies ascend into the medium to high GHz region. As frequency goes up, active probes become less and less accurate due to capacitive loading of circuit nodes, and capacitive coupling of stray signals into the probe from nearby circuit traces. We have found that Laser Voltage Imaging (LVi) offers an alternative measurement technique that can avoid these problems. But our work also showed that there are unusual failure signatures which appear as signal frequencies go up. A combination of LVI and RF-SDL was found to yield the best result.

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Magnetic Current Imaging Techniques: Comparative Case Studies

ISTFA 2004: Conference Proceedings from the 30th International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2004p0029 ◽

2004 ◽

Author(s):

Olivier Crépel ◽

Philippe Descamps ◽

Patrick Poirier ◽

Romain Desplats ◽

Philippe Perdu ◽

...

Keyword(s):

Magnetic Field ◽

Integrated Circuits ◽

Case Studies ◽

Flip Chip ◽

Imaging Techniques ◽

Optimal Domain ◽

Magnetic Current ◽

Comparative Case Studies ◽

Current Flows

Abstract Magnetic field based techniques have shown great capabilities for investigation of current flows in integrated circuits (ICs). After reviewing the performances of SQUID, GMR (hard disk head technologies) and MTJ existing sensors, we will present results obtained on various case studies. This comparison will show the benefit of each approach according to each case study (packaged devices, flip-chip circuits, …). Finally we will discuss on the obtained results to classify current techniques, optimal domain of applications and advantages.

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