Ultra-Low-Power and Performance-Improved Logic Circuit Using Hybrid TFET-MOSFET Standard Cells Topologies and Optimized Digital Front-End Process

Author(s):  
Zhixuan Wang ◽  
Le Ye ◽  
Qianqian Huang ◽  
Kaixuan Du ◽  
Zhichao Tan ◽  
...  
2010 ◽  
Vol E93-C (6) ◽  
pp. 785-795
Author(s):  
Sung-Jin KIM ◽  
Minchang CHO ◽  
SeongHwan CHO
Keyword(s):  
Rfid Tag ◽  

Author(s):  
T P Shivangi ◽  
M. Rahimi ◽  
Gaetano Gargiulo ◽  
Binsu J Kailath ◽  
Tara Julia Hamilton

2018 ◽  
Vol 7 (2.16) ◽  
pp. 19
Author(s):  
T Yugendra Chary ◽  
S Anitha ◽  
M Alamillo ◽  
Ameet Chavan

For efficient ultra-low power IoT applications, working with various communication devices and sensors which operating voltages  from subthreshold to superthreshold levels which requires wide variety of robust level converters for signal interfacing with low power dissipation. This paper proposes two topologies of level converter circuits that offer dramatic improvement in power and performance when compared to the existing level converters that shift signals from sub to super threshold levels for IoT applications. At 250 mV, the first proposed circuit - a modification of a tradition al current mirror level converter - offers the best energy efficiency with approximately seven times less energy consumption per operation than the existing design, but suffers from a slight reduction in performance.  However, a second proposed circuit - based on a two-stage level converter - at the same voltage enhances performance by several orders of magnitude while still maintaining a modest improvement in energy efficiency.  The Energy Delay Products (EDP) of the two proposed designs are equivalent and are approximately four times better than the best existing design.  Consequently, the two circuit options either optimizes power or performance with improved overall EDP.  


Sign in / Sign up

Export Citation Format

Share Document