A new family of very low-voltage analog circuits based on quasi-floating-gate transistors

Author(s):  
J. Ramirez-Angulo ◽  
C.A. Urquidi ◽  
R. Gonzalez-Carvajal ◽  
A. Torralba ◽  
A. Lopez-Martin
Author(s):  
P. John Paul ◽  
Raj N

In this paper, non-conventional circuit design techniques has been reviewed. The techniques discussed are widely used for realizing low voltage low power analog circuits. The discussed techniques in this paper are: Bulk Driven, Floating and Quasi-floating Gate followed by operating of Bulk Driven MOSFET in Floating and Quasi-floating Gate mode. In all the approach, the threshold voltage restriction is removed or reduced from the input signal path thereby reducing the power consumption. However, the adverse effect lies is terms of reduced performance parameters of MOSFET compared to conventional gate driven MOSFET parameters as shown in this paper through simulation results. The comparative analysis of MOSFET parameters results in encouragement of two approaches: Quasi-floating Gate and Bulk Driven Quasi-floating Gate MOSFET. Each of these approaches has its advantage in specific domains. Further in this paper, an Operational Transconductance Amplifier is proposed which use the Bulk Driven Quasi-floating Gate MOSFET technique and the same is amplifier under similar conditions is also realized using Bulk Driven MOSFET so as to highlight the advantage of Bulk Driven  Quasi-floating Gate MOSFET over Bulk Driven MOSFET. All the performances metrics are achieved with the help of HSpice simulator using MOSFET models of 180nm technology provided by UMC.


2006 ◽  
Vol 14 (10) ◽  
pp. 1151-1156 ◽  
Author(s):  
M. Maymandi-Nejad ◽  
M. Sachdev
Keyword(s):  

2004 ◽  
Vol 830 ◽  
Author(s):  
P. Dimitrakis ◽  
P. Normand

ABSTRACTCurrent research directions and recent advances in the area of semiconductor nanocrystal floating-gate memory devices are herein reviewed. Particular attention is placed on the advantages, limitations and perspectives of some of the principal new alternatives suggested for improving device performance and reliability. The attractive option of generating Si nanocrystal memories by ion-beam-synthesis (IBS) is discussed with emphasis on the ultra-low-energy (ULE) regime. Pertinent issues related to the fabrication of low-voltage memory cells and the integration of the ULE-IBS technique in manufactory environment are discussed. The effect on device performance of parasitic transistors that form at the channel corner of shallow trench isolated transistors is described in details. It is shown that such parasitic transistors lead to a substantial degradation of the electrical properties of the intended devices and dominates the memory behavior of deep submicronic cells.


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