Operational transconductance amplifier-based comparator for high frequency applications using 22 nm FinFET technology

<p><span>Fin field-effect transistor (FinFET) based analog circuits are gaining importance over metal oxide semiconductor field effect transistor (MOSFET) based circuits with stability and high frequency operations. Comparator that forms the sub block of most of the analog circuits is designed using operational transconductance amplifier (OTA). The OTA is designed using new design procedures and the comparator circuit is designed integrating the sub circuits with OTA. The building blocks of the comparator design such as input level shifter, differential pair with cascode stage and class AB amplifier for output swing are designed and integrated. Folded cascode circuit is used in the feedback path to maintain the common mode input value to a constant, so that the differential pair amplifies the differential signal. The gain of the comparator is achieved to be greater than 100 dB, with phase margin of 65°, common mode rejection ratio (CMRR) of above 70 dB and output swing from rail to rail. The circuit provides unity gain bandwidth of 5 GHz and is suitable for high sampling rate data converter circuits.</span></p>

A low power comparator utilizing MTSCStack, DTTS, and bulk-driven techniques

Comparator is one of the main blocks that play a vital task in the performance of analog to digital converters (ADC) in all modern technology devices. High-speed devices with low voltage and low power are considered essential for industrial applications. The design of a low-power comparator with high speed is required to accomplish the requirements mostly in electronic devices that are necessary for high-speed ADCs. However, a high-speed device that leads the scaling down of CMOS process technology will consume more power. Thus, power reduction techniques such as multi-threshold super cut-off stack (MTSCStack), dual-threshold transistor stacking (DTTS), a bulk-driven, and a bulk-driven differential pair were studied in this work. This study aims to find and build the combination of these techniques to produce a comparator that can operate in low power without compromising existing performance using the 0.13-µm CMOS process. A comparator with a combination of MTSCStack, DTTS, and NMOS bulk-driven differential pair shows the most promising result of 6.29 µW for static power, 17.15 µW for dynamic power, and 23.44 µW for total power.

A Highly Robust Binary Neural Network Inference Accelerator Based on Binary Memristors

Since memristor was found, it has shown great application potential in neuromorphic computing. Currently, most neural networks based on memristors deploy the special analog characteristics of memristor. However, owing to the limitation of manufacturing process, non-ideal characteristics such as non-linearity, asymmetry, and inconsistent device periodicity appear frequently and definitely, therefore, it is a challenge to employ memristor in a massive way. On the contrary, a binary neural network (BNN) requires its weights to be either +1 or −1, which can be mapped by digital memristors with high technical maturity. Upon this, a highly robust BNN inference accelerator with binary sigmoid activation function is proposed. In the accelerator, the inputs of each network layer are either +1 or 0, which can facilitate feature encoding and reduce the peripheral circuit complexity of memristor hardware. The proposed two-column reference memristor structure together with current controlled voltage source (CCVS) circuit not only solves the problem of mapping positive and negative weights on memristor array, but also eliminates the sneak current effect under the minimum conductance status. Being compared to the traditional differential pair structure of BNN, the proposed two-column reference scheme can reduce both the number of memristors and the latency to refresh the memristor array by nearly 50%. The influence of non-ideal factors of memristor array such as memristor array yield, memristor conductance fluctuation, and reading noise on the accuracy of BNN is investigated in detail based on a newly memristor circuit model with non-ideal characteristics. The experimental results demonstrate that when the array yield α ≥ 5%, or the reading noise σ ≤ 0.25, a recognition accuracy greater than 97% on the MNIST data set is achieved.

Comparative Analysis of CNTFET Models through the Design of a Differential Amplifier

In this paper we compare simulation results on a differential pair circuit using a CNTFET model, already proposed by us, with the result obtained using Stanford model. We study the case of differential pair with differential input and single ended output as core of a 50 GHz amplifier for mm waves band. We consider the case of a CNTFET having a single CNT tube with indices (19,0) and 25 nm long. For this circuit we present result for its main parameters: gain, input impedance, output impedance, noise and distortion. Since the Stanford model includes fixed capacitance, for comparison we applied the same capacitance on our model. Since this capacitances dominate the high frequency cut, results are not much different, except for the lack of noise modelling in the Stanford model.

Hybrid Cross Coupled Differential Pair and Colpitts Quadrature Digitally Controlled Oscillator Architecture

Growing importance of wireless communication systems forces reduction of power consumption of the designed integrated circuits. The paper focuses on minimization of power consumption in a digitally controlled oscillator (DCO) that can be employed as oscillator in GPS/Galileo receiver. The new hybrid architecture of DCO combines good phase noise performance of a Colpitts oscillator and relaxed startup conditions of a cross-coupled differential pair oscillator. The proposed new DCO generates a quadrature signal in a current reused frequency divider. Such solution allows of the dissipated power to be reduced. The DCO has been implemented in 110 nm CMOS technology. It generates output signal in frequency range from 1.52 GHz to 1.6 GHz and consumes 1.1 mW from 1.5 V supply voltage. The measured phase noise equals −116 dBc/Hz at 1 MHz offset from 1.575 GHz output signal.

An Analog Voltage Similarity Circuit with a Bell-Shaped Power Consumption

This paper presents a voltage similarity circuit (bump circuit) based on a novel voltage correlator. The proposed circuit is characterized by a power consumption which depends on the similarity between the two inputs. The sensitivity of the bump circuit and the power consumption are at the highest values when the inputs are equal. As the similarity between the input voltages decreases, the total current consumption decreases with a bell-shaped behavior. The proposed bump circuit is very simple in design, made of a new voltage correlator circuit in combination with a differential pair and mimics the behavior of the classical bump circuit. The voltage correlator was implemented using AMS−350nm CMOS technology. Simulation and measurement results suggests that a low power consumption may be achieved if the circuit is used in applications where the input signals have large dissimilarity for most of the circuit operation.