A 10 GB/S EQUALIZER WITH INTEGRATED CLOCK AND DATA RECOVERY FOR OPTICAL COMMUNICATION SYSTEMS

2005 ◽  
Vol 15 (03) ◽  
pp. 525-548 ◽  
Author(s):  
D. S. MCPHERSON ◽  
H. TRAN ◽  
P. POPESCU
Keyword(s):  
Communication Systems ◽  
High Speed ◽  
Automatic Gain Control ◽  
Polarization Mode Dispersion ◽  
Gain Control ◽  
Clock And Data Recovery ◽  
Data Recovery ◽  
Decision Feedback ◽  
Bicmos Technology ◽  
Feedforward Equalizer

A 10 Gb/s analog continuous-time equalizer with integrated clock and data recovery circuit is presented. It is designed to recover signals degraded by chromatic and polarization mode dispersion. The key components in the design are a feedforward equalizer and a decision feedback equalizer, the parameters of which are electronically adjustable. Both circuit blocks are fully described and characterized with emphasis on minimizing self-induced distortion and maximizing high-speed performance. In addition to the equalizer and the clock and data recovery, the circuit also includes an integrated automatic gain control. The circuit is implemented in a commercial 0.18 μm SiGe BiCMOS technology and consumes 900 mW. The capacity of the equalizer to mitigate signal impairments is demonstrated using three electrically generated channels.

scholarly journals Adaptive Data-Transition Decision Feedback Equalizers For High-Speed Serial Links

2021 ◽  
Author(s):  
Yue Li
Keyword(s):  
High Speed ◽  
Low Frequency ◽  
Clock And Data Recovery ◽  
Frequency Difference ◽  
Data Recovery ◽  
Decision Feedback ◽  
Loop Unrolling ◽  
Frequency Components ◽  
Eye Opening ◽  
Simulation Results

This dissertation investigates adaptive decision feedback equalizers for high-speed serial data links.<div>An adaptive data-transition decision feedback equalizer (DT-DFE) was developed. The DT-DFE boosts the eye-opening of the high-frequency components of data without attenuating their low-frequency counterparts. Reference voltages were obtained by transmitting consecutive 1s and 0s and measuring the output of the continuous-time linear equalizer using a pair of successive approximation register analog-to-digital converters in a training phase. It uses loop unrolling to detect data transitions, activate tap-tuning, launch DFE, and combat timing constraints. The performance of the DT-DFE and its advantages over commonly used data-state DFE were validated using the schematic-level simulation results of 5 Gbps backplane links.<br></div><div>A new adaptive DT-DFE with edge-emphasis (EE) taps and raised references was developed. Loop-unrolling was further developed for DT-DFE with EE-taps. The reference voltages were raised beyond that set by the low-frequency components of data to increase vertical eye-opening. Clock and data recovery was performed using 4x oversampling. The DT-DFE was validated using the schematiclevel simulation results of 10 Gbps backplane links.<br></div><div>A pre-skewed bi-directional gated delay line (BDGDL) bang-bang frequency difference-to-digital converter and a BDGDL integrating frequency difference-todigital converter (iFDDC) were proposed for clock and data recovery. Both frequency difference detectors feature all-digital realization, low power consumption, and high-speed operation. The built-in integration of iFDDC results in a zero static frequency error and the first-order noise-shaping of the quantization errors of the BDGDL and digitally-controlled oscillators. Their effectiveness was validated using schematic-level simulation results of 5-GHz frequency-locked loops.<br></div><div>All systems validating the proposed adaptive DFE and frequency-difference detectors were designed in TSMC’s 65 nm CMOS technology and analyzed using Spectre from Cadence Design Systems. <br></div>

scholarly journals Adaptive Data-Transition Decision Feedback Equalizers For High-Speed Serial Links

2021 ◽  
Author(s):  
Yue Li
Keyword(s):  
High Speed ◽  
Low Frequency ◽  
Clock And Data Recovery ◽  
Frequency Difference ◽  
Data Recovery ◽  
Decision Feedback ◽  
Loop Unrolling ◽  
Frequency Components ◽  
Eye Opening ◽  
Simulation Results

This dissertation investigates adaptive decision feedback equalizers for high-speed serial data links.<div>An adaptive data-transition decision feedback equalizer (DT-DFE) was developed. The DT-DFE boosts the eye-opening of the high-frequency components of data without attenuating their low-frequency counterparts. Reference voltages were obtained by transmitting consecutive 1s and 0s and measuring the output of the continuous-time linear equalizer using a pair of successive approximation register analog-to-digital converters in a training phase. It uses loop unrolling to detect data transitions, activate tap-tuning, launch DFE, and combat timing constraints. The performance of the DT-DFE and its advantages over commonly used data-state DFE were validated using the schematic-level simulation results of 5 Gbps backplane links.<br></div><div>A new adaptive DT-DFE with edge-emphasis (EE) taps and raised references was developed. Loop-unrolling was further developed for DT-DFE with EE-taps. The reference voltages were raised beyond that set by the low-frequency components of data to increase vertical eye-opening. Clock and data recovery was performed using 4x oversampling. The DT-DFE was validated using the schematiclevel simulation results of 10 Gbps backplane links.<br></div><div>A pre-skewed bi-directional gated delay line (BDGDL) bang-bang frequency difference-to-digital converter and a BDGDL integrating frequency difference-todigital converter (iFDDC) were proposed for clock and data recovery. Both frequency difference detectors feature all-digital realization, low power consumption, and high-speed operation. The built-in integration of iFDDC results in a zero static frequency error and the first-order noise-shaping of the quantization errors of the BDGDL and digitally-controlled oscillators. Their effectiveness was validated using schematic-level simulation results of 5-GHz frequency-locked loops.<br></div><div>All systems validating the proposed adaptive DFE and frequency-difference detectors were designed in TSMC’s 65 nm CMOS technology and analyzed using Spectre from Cadence Design Systems. <br></div>

Design of Robust Quantizers for Low-Bit Analog-to-Digital Converters for Gaussian Source

2019 ◽  
Vol 28 (supp01) ◽  
pp. 1940002 ◽  
Author(s):  
Milan R. Dinčić ◽  
Zoran H. Perić ◽  
Dragan B. Denić ◽  
Zoran Stamenković
Keyword(s):  
Energy Consumption ◽  
Communication Systems ◽  
Mimo Systems ◽  
Automatic Gain Control ◽  
Gain Control ◽  
Analog To Digital Converters ◽  
Signal Power ◽  
Analog To Digital ◽  
Wide Range ◽  
Gaussian Source

This paper considers the design of robust logarithmic [Formula: see text]-law companding quantizers for the use in analog-to-digital converters (ADCs) in communication system receivers. The quantizers are designed for signals with the Gaussian distribution, since signals at the receivers of communication systems can be very well modeled by this type of distribution. Furthermore, linearization of the logarithmic [Formula: see text]-law companding function is performed to simplify hardware implementation of the quantizers. In order to reduce energy consumption, low-resolution quantizers are considered (up to 5 bits per sample). The main advantage of these quantizers is high robustness — they can provide approximately constant SNR in a wide range of signal power (this is very important since the signal power at receivers can vary in wide range, due to fading and other transmission effects). Using the logarithmic [Formula: see text]-law companding quantizers there is no need for using automatic gain control (AGC), which reduces the implementation complexity and increases the speed of the ADCs due to the absence of AGC delay. Numerical results show that the proposed model achieves good performances, better than a uniform quantizer, especially in a wide range of signal power. The proposed low-bit ADCs can be used in MIMO and 5G massive MIMO systems, where due to very high operating frequencies and a large number of receiving channels (and consequently a large number of ADCs), the reduction of ADC complexity and energy consumption becomes a significant goal.

scholarly journals A Robust High Speed Serial PHY Architecture With Feed-Forward Correction Clock and Data Recovery

2009 ◽  
Vol 44 (7) ◽  
pp. 1914-1926 ◽  
Author(s):  
William Redman-White ◽  
Martin Bugbee ◽  
Steve Dobbs ◽  
Xinyan Wu ◽  
Richard Balmford ◽  
...  
Keyword(s):  
High Speed ◽  
Clock And Data Recovery ◽  
Data Recovery ◽  
Feed Forward

scholarly journals 10-GHz Fully Differential Sallen–Key Lowpass Biquad Filters in 55nm SiGe BiCMOS Technology

Electronics ◽  
2020 ◽  
Vol 9 (4) ◽  
pp. 563
Author(s):  
Francesco Centurelli ◽  
Pietro Monsurrò ◽  
Giuseppe Scotti ◽  
Pasquale Tommasino ◽  
Alessandro Trifiletti
Keyword(s):  
Communication Systems ◽  
Power Efficiency ◽  
High Speed ◽  
Closed Loop ◽  
Dynamic Range ◽  
Data Converters ◽  
Fully Differential ◽  
Biquad Filter ◽  
Bicmos Technology ◽  
Sige Bicmos

Multi-GHz lowpass filters are key components for many RF applications and are required for the implementation of integrated high-speed analog-to-digital and digital-to-analog converters and optical communication systems. In the last two decades, integrated filters in the Multi-GHz range have been implemented using III-V or SiGe technologies. In all cases in which the size of passive components is a concern, inductorless designs are preferred. Furthermore, due to the recent development of high-speed and high-resolution data converters, highly linear multi-GHz filters are required more and more. Classical open loop topologies are not able to achieve high linearity, and closed loop filters are preferred in all applications where linearity is a key requirement. In this work, we present a fully differential BiCMOS implementation of the classical Sallen Key filter, which is able to operate up to about 10 GHz by exploiting both the bipolar and MOS transistors of a commercial 55-nm BiCMOS technology. The layout of the biquad filter has been implemented, and the results of post-layout simulations are reported. The biquad stage exhibits excellent SFDR (64 dB) and dynamic range (about 50 dB) due to the closed loop operation, and good power efficiency (0.94 pW/Hz/pole) with respect to comparable active inductorless lowpass filters reported in the literature. Moreover, unlike other filters, it exploits the different active devices offered by commercial SiGe BiCMOS technologies. Parametric and Monte Carlo simulations are also included to assess the robustness of the proposed biquad filter against PVT and mismatch variations.

scholarly journals A Low-Complexity Decision Feedforward Equalizer Architecture for High-Speed Receivers on Highly Dispersive Channels

2013 ◽  
Vol 2013 ◽  
pp. 1-10 ◽  
Author(s):  
Ariel L. Pola ◽  
Juan E. Cousseau ◽  
Oscar E. Agazzi ◽  
Mario R. Hueda
Keyword(s):  
Error Probability ◽  
High Speed ◽  
Low Complexity ◽  
Decision Feedback ◽  
Decision Feedback Equalizer ◽  
Channel Memory ◽  
Exponential Increase ◽  
Dispersive Channels ◽  
Large Memory ◽  
Feedforward Equalizer

This paper presents an improved decision feedforward equalizer (DFFE) for high speed receivers in the presence of highly dispersive channels. This decision-aided equalizer technique has been recently proposed for multigigabit communication receivers, where the use of parallel processing is mandatory. Well-known parallel architectures for the typical decision feedback equalizer (DFE) have a complexity that grows exponentially with the channel memory. Instead, the new DFFE avoids that exponential increase in complexity by using tentative decisions to cancel iteratively the intersymbol interference (ISI). Here, we demostrate that the DFFE not only allows to obtain a similar performance to the typical DFE but it also reduces the compelxity in channels with large memory. Additionally, we propose a theoretical approximation for the error probability in each iteration. In fact, when the number of iteration increases, the error probability in the DFFE tends to approach the DFE. These benefits make the DFFE an excellent choice for the next generation of high-speed receivers.

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