On-chip ESD protection circuit design with novel substrate-triggered SCR device in sub-quarter-micron CMOS process

2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353) ◽

10.1109/iscas.2002.1010757 ◽

2003 ◽

Author(s):

Ming-Dou Ker ◽

Kuo-Chun Hsu

Keyword(s):

Circuit Design ◽

Cmos Process ◽

Esd Protection ◽

Protection Circuit ◽

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Substrate-triggered technique for on-chip ESD protection design in a 0.18-μm salicided CMOS process

IEEE Transactions on Electron Devices ◽

10.1109/ted.2003.812495 ◽

2003 ◽

Vol 50 (4) ◽

pp. 1050-1057 ◽

Author(s):

Ming-Dou Ker ◽

Tung-Yang Chen

Keyword(s):

Cmos Process ◽

Esd Protection ◽

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Layout and Technology Influences on ESD Protection Circuit Design

On-Chip ESD Protection for Integrated Circuits - The International Series in Engineering and Computer Science ◽

10.1007/0-306-47618-5_7 ◽

2006 ◽

pp. 171-218

Keyword(s):

Circuit Design ◽

Esd Protection ◽

Protection Circuit

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MOS-Bounded Diodes for On-Chip ESD Protection in Deep Submicron CMOS Process

IEICE Transactions on Electronics ◽

10.1093/ietele/e88-c.3.429 ◽

2005 ◽

Vol E88-C (3) ◽

pp. 429-436 ◽

Author(s):

M.-D. KER

Keyword(s):

Deep Submicron ◽

Cmos Process ◽

Esd Protection ◽

Submicron Cmos ◽

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Function-based ESD protection circuit design verification for BGA pad-ring array

2015 IEEE 11th International Conference on ASIC (ASICON) ◽

10.1109/asicon.2015.7516902 ◽

2015 ◽

Author(s):

Li Wang ◽

Rui Ma ◽

Fei Lu ◽

Albert Wang ◽

Zongyu Dong ◽

...

Keyword(s):

Circuit Design ◽

Design Verification ◽

Esd Protection ◽

Protection Circuit

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On-chip ESD protection design for GHz RF integrated circuits by using polysilicon diodes in sub-quarter-micron CMOS process

2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517) ◽

10.1109/vtsa.2001.934529 ◽

2002 ◽

Author(s):

Chyh-Yih Chang ◽

Ming-Dou Ker

Keyword(s):

Integrated Circuits ◽

Cmos Process ◽

Rf Integrated Circuits ◽

Esd Protection ◽

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Concept and extraction method of ESD-critical parameters for function-based layout-level ESD protection circuit design verification

ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753) ◽

10.1109/aspdac.2004.1337685 ◽

2005 ◽

Author(s):

R.Y. Zhan ◽

H.G. Feng ◽

Q. Wu ◽

X.K. Guan ◽

G. Chen ◽

...

Keyword(s):

Circuit Design ◽

Extraction Method ◽

Critical Parameters ◽

Design Verification ◽

Esd Protection ◽

Protection Circuit

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Substrate-triggered SCR device for on-chip ESD protection in fully silicided sub-0.25-μm CMOS process

IEEE Transactions on Electron Devices ◽

10.1109/ted.2003.809028 ◽

2003 ◽

Vol 50 (2) ◽

pp. 397-405 ◽

Author(s):

Ming-Dou Ker ◽

Kuo-Chun Hsu

Keyword(s):

Cmos Process ◽

Esd Protection ◽

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On-chip ESD protection design by using polysilicon diodes in CMOS process

IEEE Journal of Solid-State Circuits ◽

10.1109/4.913746 ◽

2001 ◽

Vol 36 (4) ◽

pp. 676-686 ◽

Author(s):

Ming-Dou Ker ◽

Tung-Yang Chen ◽

Tai-Ho Wang ◽

Chung-Yu Wu

Keyword(s):

Cmos Process ◽

Esd Protection ◽

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Design of a Distributed Amplifier with On-chip ESD Protection Circuit in 130 nm SOI CMOS Technology

2007 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems ◽

10.1109/smic.2007.322782 ◽

2007 ◽

Author(s):

M. Moussa ◽

M. Kaamouchi ◽

G. Wybo ◽

A. Bens ◽

J.-p. Raskin ◽

...

Keyword(s):

Cmos Technology ◽

Distributed Amplifier ◽

Esd Protection ◽

Protection Circuit ◽

On Chip ◽

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EOS/ESD protection circuit design for deep submicron SOI technology

Electrical Overstress/Electrostatic Discharge Symposium Proceedings ◽

10.1109/eosesd.1995.478287 ◽

1995 ◽

Author(s):

S. Ramaswamy ◽

P. Raha ◽

E. Rosenbaum ◽

Sung-Mo Kang

Keyword(s):

Circuit Design ◽

Deep Submicron ◽

Esd Protection ◽

Protection Circuit ◽

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