Doping Profile Optimization for Power Devices Using Topology Optimization

2018 ◽  
Vol 65 (9) ◽  
pp. 3869-3877
Author(s):  
Katsuya Nomura ◽  
Tsuguo Kondoh ◽  
Tsuyoshi Ishikawa ◽  
Shintaro Yamasaki ◽  
Kentaro Yaji ◽  
...  
Author(s):  
D.D. Rathman ◽  
M.A. Hollis ◽  
R.A. Murphy ◽  
A.L. McWhorter ◽  
M.J. McNamara

MRS Advances ◽  
2019 ◽  
Vol 4 (44-45) ◽  
pp. 2377-2382
Author(s):  
J Pan ◽  
S. Afroz ◽  
N. Crain ◽  
W. Henning ◽  
J. Oliver ◽  
...  

AbstractIn this paper we report high voltage MOS and Schottky Diode CV techniques for silicon and SiC power devices. 4H Silicon carbide is a wide bandgap semiconductor suitable for high voltage power electronics and RF applications due to high avalanche breakdown critical electric field, and thermal conductivity. The performance of various power devices, which may include MOSFET and Static Induction Transistor (SIT), can be affected by the deep level traps in the substrate and the oxide interfacial defects. We have characterized deep level trap (High Voltage Schottky Diode HF CV) and oxide interface trap densities (High Voltage HF MOS CV), measured the device channel doping profile for both 4H SiC and silicon, gate metal workfunction, and simulated the effects on DC/AC performance.


Author(s):  
Giovanni Stracquadanio ◽  
Concetta Drago ◽  
Vittorio Romano ◽  
Giuseppe Nicosia

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