Automatic test plan generation for analog and mixed signal integrated circuits using partial activation and high level simulation

2002 ◽  
Author(s):  
N. Ravindranath ◽  
G.N. Nandakumar ◽  
K. Srinivasa Rao
Keyword(s):  
Integrated Circuits ◽  
Test Plan ◽  
Automatic Test ◽  
Mixed Signal ◽  
Plan Generation ◽  
Partial Activation ◽  
High Level ◽  
Test Plan Generation

scholarly journals EXPERT SYSTEMS AND TEST PLAN GENERATION

1990 ◽  
Author(s):  
ΙΩΑΝΝΗΣ ΠΑΠΑΒΑΣΙΛΕΙΟΥ
Keyword(s):  
Expert Systems ◽  
Test Plan ◽  
Plan Generation ◽  
Test Plan Generation

scholarly journals Design automation of ΔΣ switched capacitor modulators using spice and MATLAB

2014 ◽  
Vol 11 (1) ◽  
pp. 47-59
Author(s):  
Dejan Mirkovic ◽  
Predrag Petkovic
Keyword(s):  
Integrated Circuits ◽  
Design Automation ◽  
Low Cost ◽  
Signal Design ◽  
Time Saving ◽  
Mixed Signal ◽  
Working Environments ◽  
High Level ◽  
Technology Processes ◽  
Simulation Time

Concerning the fact that the design of contemporary integrated circuits (IC) is practically impossible without using sophisticated Electronic Design Automation (EDA) software, this paper gives some interesting thoughts and considerations about that issue. As technology processes advances on year basis consequently EDA industry is forced to follow this trend as well. This, on the other hand, requires IC designer to frequently and efficiently accommodate to new working environments. Authors of this paper suggest a method for high level circuit analysis that is based on using common (open source or low cost) circuit simulators but precise and fast enough to meet requirements imposed by demanding mixed-signal blocks. The paper demonstrates the proposed EDA procedure on an example of second order ?? modulator design. It illustrates considerable simulation time saving which is more than welcome in a world of analogue and mixed-signal design.

scholarly journals A Modified Approach to Test Plan Generation for Combinational Logic Blocks

VLSI Design ◽  
1996 ◽  
Vol 4 (3) ◽  
pp. 243-256
Author(s):  
Anupam Basu ◽  
Dilip K. Banerji ◽  
Amit Basu ◽  
T. C. Wilson ◽  
Jay C. Majithia
Keyword(s):  
Vlsi Circuits ◽  
Testing Time ◽  
Combinational Logic ◽  
Test Plan ◽  
Crucial Step ◽  
Plan Generation ◽  
Test Methodology ◽  
Test Plan Generation ◽  
Total Testing Time ◽  
Logic Blocks

Generation of test plans is a crucial step for testing VLSI circuits. This paper presents a modified approach to test plan generation for the BILBO test methodology. A few limitations of the existing approaches have been identified and methods to address these have been suggested. The proposed approach has been implemented for the general case of n-port combinational logic blocks (CLBs). However, due to limitations of space and for clarity, only 2-port CLBs are considered in this paper. For this case, the problem is modelled as a Step Scheduling Matrix and an algorithm is presented for the solution. The algorithm has been tested on a number of benchmark circuits and the results are compared with those obtained through existing methods. The effectiveness of the proposed approach is clear from the results, as it contributes to the reduction in total testing time as well as generates a larger number of test plans.

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