Distributed Sensor Network-on-Chip for Performance Optimization of Soft-Error-Tolerant Multiprocessor System-on-Chip

2016 ◽  
Vol 24 (4) ◽  
pp. 1546-1559 ◽  
Author(s):  
Weichen Liu ◽  
Wei Zhang ◽  
Xuan Wang ◽  
Jiang Xu
Keyword(s):  
Sensor Network ◽  
Performance Optimization ◽  
Network On Chip ◽  
System On Chip ◽  
Soft Error ◽  
Multiprocessor System ◽  
Distributed Sensor ◽  
Distributed Sensor Network ◽  
On Chip

scholarly journals Thermal-Aware Task Mapping on Dynamically Reconfigurable Network-on-Chip Based Multiprocessor System-on-Chip

2018 ◽  
Vol 67 (12) ◽  
pp. 1818-1834 ◽  
Author(s):  
Weichen Liu ◽  
Lei Yang ◽  
Weiwen Jiang ◽  
Liang Feng ◽  
Nan Guan ◽  
...  
Keyword(s):  
Network On Chip ◽  
System On Chip ◽  
Multiprocessor System ◽  
Task Mapping ◽  
Dynamically Reconfigurable ◽  
On Chip

3-D Mesh-Based Optical Network-on-Chip for Multiprocessor System-on-Chip

2013 ◽  
Vol 32 (4) ◽  
pp. 584-596 ◽  
Author(s):  
Yaoyao Ye ◽  
Jiang Xu ◽  
Baihan Huang ◽  
Xiaowen Wu ◽  
Wei Zhang ◽  
...  
Keyword(s):  
Optical Network ◽  
Network On Chip ◽  
System On Chip ◽  
Multiprocessor System ◽  
On Chip

scholarly journals Congestion-Aware Routing Algorithm for NoC Using Data Packets

2021 ◽  
Vol 2021 ◽  
pp. 1-11
Author(s):  
Khurshid Ahmad ◽  
Muhammad Athar Javed Sethi ◽  
Rehmat Ullah ◽  
Imran Ahmed ◽  
Amjad Ullah ◽  
...  
Keyword(s):  
Routing Algorithm ◽  
Network On Chip ◽  
Routing Algorithms ◽  
System On Chip ◽  
Multiprocessor System ◽  
Data Packets ◽  
Communication Framework ◽  
Using Data ◽  
On Chip ◽  
Congestion Aware

Network on Chip (NoC) is a communication framework for the Multiprocessor System on Chip (MPSoC). It is a router-based communication system. In NoC architecture, nodes of MPSoC are communicating through the network. Different routing algorithms have been developed by researchers, e.g., XY, intermittent XY, DyAD, and DyXY. The main problems in these algorithms are congestion and faults. Congestion and faults cause delay, which degrades the performance of NoC. A congestion-aware algorithm is used for the distribution of traffic over NoC and for the avoidance of congestion. In this paper, a congestion-aware routing algorithm is proposed. The algorithm works by sending congestion information in the data packet. The algorithm is implemented on a 4 × 4 mesh NoC using FPGA. The proposed algorithm decreases latency, increases throughput, and uses less bandwidth in sharing congestion information between routers in comparison to the existing congestion-aware routing algorithms.

A Torus-Based Hierarchical Optical-Electronic Network-on-Chip for Multiprocessor System-on-Chip

2012 ◽  
Vol 8 (1) ◽  
pp. 1-26 ◽  
Author(s):  
Yaoyao Ye ◽  
Jiang Xu ◽  
Xiaowen Wu ◽  
Wei Zhang ◽  
Weichen Liu ◽  
...  
Keyword(s):  
Network On Chip ◽  
System On Chip ◽  
Multiprocessor System ◽  
Electronic Network ◽  
On Chip
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