Low Complexity Stopping Criterion for LDPC Code Decoders

2005 ◽  
Author(s):  
F. Kienle ◽  
N. Wehn
Keyword(s):  
Ldpc Code ◽  
Low Complexity ◽  
Stopping Criterion

scholarly journals Before convergence early stopping criterion for inner LDPC code in DVB standards

2015 ◽  
Vol 51 (1) ◽  
pp. 114-116 ◽  
Author(s):  
C. Marchand ◽  
E. Boutillon
Keyword(s):  
Ldpc Code ◽  
Stopping Criterion ◽  
Early Stopping

The Design of Low Complexity Decoder Based on DVB-S2 LDPC

2012 ◽  
Vol 239-240 ◽  
pp. 911-914
Author(s):  
Zhong Xun Wang ◽  
Shuang Shuang Yin
Keyword(s):  
Hardware Implementation ◽  
Ldpc Code ◽  
Low Complexity ◽  
Bch Code ◽  
Digital Video Broadcasting ◽  
Video Broadcasting ◽  
Uniform Quantization ◽  
Point Representation ◽  
Simulation Results ◽  
Decoder Complexity

An improved codeword construction method was used to encode the BCH code and LDPC code in this paper according to the latest standard defined by digital video broadcasting standard(DVB), and moreover the data overflow problem was solved. The LDPC code was decoded by the reduced complexity Min-Sum decoding algorithm, in which the coefficient was studied. Fixed-point representation and decoder quantization were proposed and simulation results show that 6-bits and 16-bits uniform quantization can make close to the performance of unquantized decoder, which reduces the decoder complexity for hardware implementation.

A BP Decoding Algorithm Based on Nodes Residual for LDPC Codes and its Hardware Implementation

2011 ◽  
Vol 128-129 ◽  
pp. 7-10
Author(s):  
Zhong Xun Wang ◽  
Xing Cheng Wang ◽  
Fang Qiang Zhu
Keyword(s):  
Hardware Implementation ◽  
Belief Propagation ◽  
Dynamic Scheduling ◽  
Ldpc Codes ◽  
Ldpc Code ◽  
Low Complexity ◽  
Decoding Algorithm ◽  
Fast Decoding ◽  
Good For

We researched BP decoding algorithm based on variable-to-check information residual for LDPC code (VC-RBP) in this paper. It is a dynamic scheduling belief propagation using residuals, and has some advantages，such as fast decoding, good performance, and low complexity. It is similar to residual belief propagation (RBP),but has some difference in computing the residual message. This paper further optimized the new algorithm on DSP of TMS320dm6446, and it is good for hardware implementation.

scholarly journals Design of Quasi-Cyclic Low Density Parity Check Decoder Using Optimized Min-Sum Algorithm

2018 ◽  
Vol 7 (03) ◽  
pp. 23781-23784
Author(s):  
Rajarshini Mishra
Keyword(s):  
Variance Estimation ◽  
Cyclic Codes ◽  
Ldpc Codes ◽  
Ldpc Code ◽  
Low Complexity ◽  
Low Density ◽  
Parity Check ◽  
Decoding Algorithm ◽  
Low Density Parity Check ◽  
Xilinx Fpga

Low-density parity-check (LDPC) have been shown to have good error correcting performance approaching Shannon’s limit. Good error correcting performance enables efficient and reliable communication. However, a LDPC code decoding algorithm needs to be executed efficiently to meet cost , time, power and bandwidth requirements of target applications. Quasi-cyclic low-density parity-check (QC-LDPC) codes are an important subclass of LDPC codes that are known as one of the most effective error controlling methods. Quasi cyclic codes are known to possess some degree of regularity. Many important communication standards such as DVB-S2 and 802.16e use these codes. The proposed Optimized Min-Sum decoding algorithm performs very close to the Sum-Product decoding while preserving the main features of the Min-Sum decoding, that is low complexity and independence with respect to noise variance estimation errors.Proposed decoder is well matched for VLSI implementation and will be implemented on Xilinx FPGA family

scholarly journals Minimum Distance Optimization with Chord Edge Growth for High Girth Non-Binary LDPC Codes

Electronics ◽  
2020 ◽  
Vol 9 (12) ◽  
pp. 2161
Author(s):  
Changcai Han ◽  
Hui Li ◽  
Weigang Chen
Keyword(s):  
Minimum Distance ◽  
Signal To Noise Ratio ◽  
High Reliability ◽  
Ldpc Codes ◽  
Full Rank ◽  
Ldpc Code ◽  
Low Complexity ◽  
High Signal ◽  
Rank Condition ◽  
Potential Applications

Short or moderate-length non-binary low-density parity-check (NB-LDPC) codes have the potential applications in future low latency and high-reliability communication thanks to the strong error correction capability and parallel decoding. Because of the existence of the error floor, the NB-LDPC codes usually cannot satisfy very low bit error rate (BER) requirements. In this paper, a low-complexity method is proposed for optimizing the minimum distance of the NB-LDPC code in a progressive chord edge growth manner. Specifically, each chord edge connecting two non-adjacent vertices is added to the Hamiltonian cycle one-by-one. For each newly added chord edge, the configuration of non-zero entries corresponding to the chord edge is determined according to the so-called full rank condition (FRC) of all cycles that are related to the chord edge in the obtained subgraph. With minor modifications to the designed method, it can be used to construct the NB-LDPC codes with an efficient encoding structure. The analysis results show that the method for designing NB-LDPC codes while using progressive chord edge growth has lower complexity than traditional methods. The simulation results show that the proposed method can effectively improve the performance of the NB-LDPC code in the high signal-to-noise ratio (SNR) region. While using the proposed scheme, an NB-LDPC code with a quite low BER can be constructed with extremely low complexity.

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