An 8-Bit 1.25-GS/s 2.5-GHz ERBW Folding-Subrange ADC with Power-Efficient Metastability Error Reduction Technique

2021 ◽  
Author(s):  
Bo-Wei Chen ◽  
Yung-Hui Chung ◽  
Chia-Ming Tsai
Keyword(s):  
Error Reduction ◽  
Reduction Technique ◽  
Power Efficient

Aperture error reduction technique for subrange SAR ADC

2016 ◽  
Author(s):  
Ying Ju ◽  
Fule Li ◽  
XiuJu He ◽  
Chun Zhang ◽  
Zhihua Wang
Keyword(s):  
Error Reduction ◽  
Reduction Technique ◽  
Sar Adc

Multiplicative Method for Reduction of Bias in Indirect Digital Measurement Result

2011 ◽  
Vol 18 (3) ◽  
pp. 481-490 ◽  
Author(s):  
Sergey Muravyov ◽  
Galina Zlygosteva ◽  
Valeriy Borikov
Keyword(s):  
Measurement Accuracy ◽  
Error Reduction ◽  
Reduction Technique ◽  
Resistance Measurement ◽  
Inverse Transformation ◽  
Digital Measurement ◽  
Active Resistance ◽  
Measurement Result ◽  
Measurement Results

Multiplicative Method for Reduction of Bias in Indirect Digital Measurement ResultThe error reduction technique, based on inverse transformation, for a shunt active resistance measurement using an ammeter and voltmeter is considered. When computing a corrected reading only multiplicative operations on two measurement results are used, namely squaring and division. The proposed method allows to increase re-sistance measurement accuracy by about two orders of magnitude what has been validated by both theoretical and experimental outcomes.

The Tilted Loop: An Error Reduction Technique for Loop Direction Finders

1969 ◽  
Vol AES-5 (6) ◽  
pp. 1005-1006
Author(s):  
H. Jenkins ◽  
R. Moss ◽  
L. Scott
Keyword(s):  
Error Reduction ◽  
Reduction Technique

Error reduction technique for four-quadrant arctangent approximations

2008 ◽  
Vol 2 (2) ◽  
pp. 133 ◽  
Author(s):  
S. Rajan ◽  
S. Wang ◽  
R. Inkol
Keyword(s):  
Error Reduction ◽  
Reduction Technique ◽  
Four Quadrant

scholarly journals COREA: Delay- and Energy-Efficient Approximate Adder Using Effective Carry Speculation

Electronics ◽  
2021 ◽  
Vol 10 (18) ◽  
pp. 2234
Author(s):  
Hyelin Seok ◽  
Hyoju Seo ◽  
Jungwon Lee ◽  
Yongtae Kim
Keyword(s):  
Machine Learning ◽  
Energy Efficiency ◽  
Energy Efficient ◽  
Logic Gates ◽  
Cmos Technology ◽  
Error Reduction ◽  
Reduction Technique ◽  
The Other ◽  
Mean Error ◽  
Error Distance

This paper presents a delay- and energy-efficient approximate adder design exploiting an effective carry speculation scheme with error reduction. The proposed scheme reduces the delay and improves the energy efficiency without any significant accuracy degradation by effectively adding the predicted carry input using the OR operation. Additionally, the error reduction technique improves the overall computation accuracy at the expense of a few logic gates. As a result, the proposed adder achieves 3.84- and 7.79-times greater energy and energy-delay product (EDP) efficiencies than the traditional adder when implemented in 65-nm CMOS technology. In particular, when jointly analyzed with hardware accuracy, our design attains 69% and 70% reductions of the energy- and EDP-normalized mean error distance (NMED) products, respectively, compared to the other approximate adders under consideration. Furthermore, the proposed adder’s efficacy over the existing adders is demonstrated by adopting it in a machine learning application.

Power-efficient metastability error reduction in CMOS flash A/D converters

1996 ◽  
Vol 31 (8) ◽  
pp. 1132-1140 ◽  
Author(s):  
C.L. Portmann ◽  
T.H.Y. Meng
Keyword(s):  
Error Reduction ◽  
Power Efficient
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