scholarly journals COREA: Delay- and Energy-Efficient Approximate Adder Using Effective Carry Speculation

Electronics ◽  
2021 ◽  
Vol 10 (18) ◽  
pp. 2234
Author(s):  
Hyelin Seok ◽  
Hyoju Seo ◽  
Jungwon Lee ◽  
Yongtae Kim
Keyword(s):  
Machine Learning ◽  
Energy Efficiency ◽  
Energy Efficient ◽  
Logic Gates ◽  
Cmos Technology ◽  
Error Reduction ◽  
Reduction Technique ◽  
The Other ◽  
Mean Error ◽  
Error Distance

This paper presents a delay- and energy-efficient approximate adder design exploiting an effective carry speculation scheme with error reduction. The proposed scheme reduces the delay and improves the energy efficiency without any significant accuracy degradation by effectively adding the predicted carry input using the OR operation. Additionally, the error reduction technique improves the overall computation accuracy at the expense of a few logic gates. As a result, the proposed adder achieves 3.84- and 7.79-times greater energy and energy-delay product (EDP) efficiencies than the traditional adder when implemented in 65-nm CMOS technology. In particular, when jointly analyzed with hardware accuracy, our design attains 69% and 70% reductions of the energy- and EDP-normalized mean error distance (NMED) products, respectively, compared to the other approximate adders under consideration. Furthermore, the proposed adder’s efficacy over the existing adders is demonstrated by adopting it in a machine learning application.

scholarly journals Design and Analysis of an Approximate Adder with Hybrid Error Reduction

Electronics ◽  
2020 ◽  
Vol 9 (3) ◽  
pp. 471
Author(s):  
Hyoju Seo ◽  
Yoon Seok Yang ◽  
Yongtae Kim
Keyword(s):  
Energy Efficient ◽  
Cmos Technology ◽  
Error Reduction ◽  
The Other ◽  
Reduction Scheme ◽  
Hardware Cost ◽  
Mean Error ◽  
The Mean ◽  
The Cost ◽  
Error Distance

This paper presents an energy-efficient approximate adder with a novel hybrid error reduction scheme to significantly improve the computation accuracy at the cost of extremely low additional power and area overheads. The proposed hybrid error reduction scheme utilizes only two input bits and adjusts the approximate outputs to reduce the error distance, which leads to an overall improvement in accuracy. The proposed design, when implemented in 65-nm CMOS technology, has 3, 2, and 2 times greater energy, power, and area efficiencies, respectively, than conventional accurate adders. In terms of the accuracy, the proposed hybrid error reduction scheme allows that the error rate of the proposed adder decreases to 50% whereas those of the lower-part OR adder and optimized lower-part OR constant adder reach 68% and 85%, respectively. Furthermore, the proposed adder has up to 2.24, 2.24, and 1.16 times better performance with respect to the mean error distance, normalized mean error distance (NMED), and mean relative error distance, respectively, than the other approximate adder considered in this paper. Importantly, because of an excellent design tradeoff among delay, power, energy, and accuracy, the proposed adder is found to be the most competitive approximate adder when jointly analyzed in terms of the hardware cost and computation accuracy. Specifically, our proposed adder achieves 51%, 49%, and 47% reductions of the power-, energy-, and error-delay-product-NMED products, respectively, compared to the other considered approximate adders.

Tunnel Transistor-Based Reliable and Energy Efficient Computing Architectures with Circuit and Architectural Co-Design at Low VDD

2017 ◽  
Vol 27 (03) ◽  
pp. 1850046 ◽  
Author(s):  
Sadulla Shaik ◽  
K. Sri Rama Krishna ◽  
Ramesh Vaddi
Keyword(s):  
Energy Efficiency ◽  
Energy Efficient ◽  
Low Voltage ◽  
Field Effect Transistors ◽  
Full Adder ◽  
Cmos Technology ◽  
Logic Design ◽  
Transmission Gate ◽  
Reliability Characteristics ◽  
Efficient Option

Tunnel field-effect transistors (TFETs) as low voltage device options have attracted recent attention for energy efficient circuit designs with CMOS technology scaling. This paper presents the circuit and architectural co-design approach for designing reliable and energy efficient architectures (adder cells) for new computing platforms at supply voltages. At circuit level TFET-based 28-transistor static logic design (28T) and 24-transistor transmission gate logic design (24T) have been explored. At architectural level, multiplexer (MUX)-based 22-transistor full adder design (22T) is proposed. Performance of TFET-based architectures have also been benchmarked with 20[Formula: see text]nm double gate Si FinFET technology. It has been seen that with FinFET technology 24T design is not effective in terms of energy efficiency and reliability (due to the large leakage currents in transmission gate logic topology). 28T design is the best in reliability perspective (in terms of reduced over shoots, full logic swing and reduced glitch duration etc.) and 22T design to be energy efficient option. It has been demonstrated in this paper that TFET’s steep slope characteristics enable the 24T design to have similar reliability characteristics like 28T design and energy efficiency like 22T design. TFET-based 22T design has [Formula: see text]91% smaller energy delay product (EDP) and [Formula: see text]84.4% less power delay product (PDP) in comparison to the low threshold voltage (LVT) FinFET 22T design at 0.2[Formula: see text]V VDD.

CNTFET-Based Ternary Logic Gates

2020 ◽  
pp. 72-92
Author(s):  
Suman Rani ◽  
Balwinder Singh
Keyword(s):  
Energy Efficiency ◽  
Comparative Analysis ◽  
Power Consumption ◽  
Integrated Circuit ◽  
Logic Gates ◽  
Cmos Technology ◽  
Nand Gate ◽  
Ternary Logic ◽  
Average Delay ◽  
Universal Gates

In the recent digital designs, there are certain circumstances where energy efficiency and ease is required, and in such situations, ternary logic (or three-valued logic) is favored. Ternary logic is an auspicious supernumerary to the conventional binary (0, 1) logic design techniques as this one is possible to attain straightforwardness and energy efficiency. This chapter deals with the comparative analysis of CMOS and CNTFET-based ternary inverter and universal gates design. The simulation result is analyzed and validated with a Hailey simulation program with integrated circuit (HSPICE) simulations. The average delay and power consumption in CNTFET-based ternary inverter have been reduced by approximately 90.3% and 48.8% respectively, as compared to CMOS-based ternary inverter design. Likewise, delay is reduced by 50% and power gets 99% reduction in ternary CNTFET NAND gate as compared to CMOS-based ternary NAND gat. It is concluded that CNFETs are faster and consume less power compared to CMOS technology.

scholarly journals HIWAEO: Hybrid Improved Whale Artificial Ecosystem Optimization Algorithm based Energy-Efficient Routing Protocol for Wireless Sensor Network

2021 ◽  
Author(s):  
R. Renuga Devi ◽  
T. Sethukarasi
Keyword(s):  
Energy Efficiency ◽  
Wireless Sensor Network ◽  
Life Span ◽  
Sensor Network ◽  
Energy Efficient ◽  
Fitness Function ◽  
Residual Energy ◽  
The Other ◽  
Sensor Nodes ◽  
Wireless Sensor

Abstract Wireless Sensor Network (WSN) is a resource constraint network that utilizes more energy for transmitting and receiving the data. Hence energy efficiency is the vital issue faced by the WSN. Besides the packet routing process consumes more energy than the other processes. Moreover, the working of WSN is based on the battery life span of sensor nodes. Thus the constrained energy source affects the life span of the network battery. To tackle this issue, we proposed a novel method known as the Hybrid Improved Whale optimization-based Artificial Ecosystem optimization method (HIWAEO). This enhances the energy efficiency of the WSN and thereby improves the routing of the network. The energy-efficient WSN can be obtained by selecting optimal cluster head (CH) and forward nodes. To select the optimal CH the proposed method estimates the fitness function which includes node degree, space between the sensor nodes and space between the CH and base station (BS), residual energy, and node centrality. This estimated fitness function arranges the sensor nodes based on their increased energy and distance from the BS and the best node is chosen as the CH. Henceforth to obtain the routing efficiency the forward nodes are selected based on their residual energy and distance. The performance of the proposed method is analyzed with the other existing approaches for three conditions of BS alignment and concluded that our proposed method outperforms all the other approaches.

scholarly journals An Energy Efficient Binary Magnitude Comparator for Nanotechnology Applications

2020 ◽  
Vol 8 (6) ◽  
pp. 430-436
Keyword(s):  
Energy Dissipation ◽  
Cellular Automata ◽  
Power Consumption ◽  
Power Dissipation ◽  
Energy Efficient ◽  
Cmos Technology ◽  
The Other ◽  
Cycle Performance ◽  
Quantum Dot Cellular Automata ◽  
Cell Numbers

Quantum-dot cellular automata (QCA) is inventive nanotechnology that suggest lesser size, lesser power consumption, with more rapid speeds and deliberated as a clarification to the scaling difficulties with CMOS technology. Physical bounds of CMOS for instance the effects of quantum and the limits of technologies like power dissipation obstruct the motion of microelectronics using consistent circuit scaling. In this paper, a 1-bit binary magnitude comparator circuit is proposed that takes down the count of QCA cells related to the previously reported design’s cell numbers. The proposed course of study involves just around 29 % of the total area as compared to the preceding design with the lesser speed and clocking cycle performance and energy dissipation also. QCA designerE tool is used for simulation and finding the parameters also. The projected magnitude comparator also compares the metrics result with some of the other preceeding patterns.

scholarly journals Distributed Transmit Power Control for Energy-Efficient Wireless-Powered Secure Communications

Sensors ◽  
2021 ◽  
Vol 21 (17) ◽  
pp. 5861
Author(s):  
Kisong Lee 
Keyword(s):  
Energy Efficiency ◽  
Power Control ◽  
Energy Efficient ◽  
Control Algorithm ◽  
Computation Time ◽  
The Other ◽  
Secure Communications ◽  
Transmit Power ◽  
Transmit Power Control ◽  
Power Control Algorithm

In this study, we consider energy-efficient wireless-powered secure communications, in which N sets of transmitter, receiver, and energy harvesting (EH) nodes exist; each EH node is allowed only to harvest energy from the transmitted signals but is not to permitted to decode information. To maximize the sum secrecy energy efficiency (SEE) of the node sets while ensuring minimum EH requirement for each EH node, we propose a distributed transmit power control algorithm using a dual method, where each transmitter adjusts its transmit power iteratively until convergence without sharing information with the other node sets. Through simulations under various environments, we show that the proposed scheme surpasses conventional schemes in terms of the sum SEE and has significantly reduced computation time compared with the optimal scheme, which suggests the effectiveness and applicability of the proposed distributed method.

Analysis Criteria for Choosing Energy Efficient High-Quality Light Sources and Luminaires

2018 ◽  
pp. 113-119
Author(s):  
Gennady Ya. Vagin ◽  
Eugene B. Solntsev ◽  
Oleg Yu. Malafeev
Keyword(s):  
Energy Efficiency ◽  
Energy Efficient ◽  
National Standards ◽  
Light Sources ◽  
The European Union ◽  
High Quality ◽  
Eu Directive ◽  
The World ◽  
A New Technique ◽  
Energy Labelling

The article analyses critera applying to the choice of energy efficient high quality light sources and luminaires, which are used in Russian domestic and international practice. It is found that national standards GOST P 54993–2012 and GOST P 54992– 2012 contain outdated criteria for determining indices and classes of energy efficiency of light sources and luminaires. They are taken from the 1998 EU Directive #98/11/EU “Electric lamps”, in which LED light sources and discharge lamps of high intensity were not included. A new Regulation of the European Union #874/2012/EU on energy labelling of electric lamps and luminaires, in which these light sources are taken into consideration, contains a new technique of determining classes of energy efficiency and new, higher classes are added. The article has carried out a comparison of calculations of the energy efficiency classes in accordance with GOST P 54993 and with Regulation #874/2012/EU, and it is found out that a calculation using GOST P 54993 gives underrated energy efficiency classes. This can lead to interdiction of export for certain light sources and luminaires, can discredit Russian domestic manufacturer light sources and does not correspond to the rules of the World Trade Organization (WTO).

Performance Analysis of TBC-ACO Routing Protocol with Existing Routing Protocols of Wireless Sensor Networks

2017 ◽  
Vol 7 (8) ◽  
pp. 169
Author(s):  
A. Radhika ◽  
D. Haritha
Keyword(s):  
Energy Efficiency ◽  
Wireless Sensor Networks ◽  
Sensor Networks ◽  
Swarm Intelligence ◽  
Routing Protocol ◽  
Routing Protocols ◽  
Energy Efficient ◽  
Sensor Nodes ◽  
Wireless Sensor ◽  
Congestion Aware

Wireless Sensor Networks, have witnessed significant amount of improvement in research across various areas like Routing, Security, Localization, Deployment and above all Energy Efficiency. Congestion is a problem of  importance in resource constrained Wireless Sensor Networks, especially for large networks, where the traffic loads exceed the available capacity of the resources . Sensor nodes are prone to failure and the misbehaviour of these faulty nodes creates further congestion. The resulting effect is a degradation in network performance, additional computation and increased energy consumption, which in turn decreases network lifetime. Hence, the data packet routing algorithm should consider congestion as one of the parameters, in addition to the role of the faulty nodes and not merely energy efficient protocols .Nowadays, the main central point of attraction is the concept of Swarm Intelligence based techniques integration in WSN.  Swarm Intelligence based Computational Swarm Intelligence Techniques have improvised WSN in terms of efficiency, Performance, robustness and scalability. The main objective of this research paper is to propose congestion aware , energy efficient, routing approach that utilizes Ant Colony Optimization, in which faulty nodes are isolated by means of the concept of trust further we compare the performance of various existing routing protocols like AODV, DSDV and DSR routing protocols, ACO Based Routing Protocol  with Trust Based Congestion aware ACO Based Routing in terms of End to End Delay, Packet Delivery Rate, Routing Overhead, Throughput and Energy Efficiency. Simulation based results and data analysis shows that overall TBC-ACO is 150% more efficient in terms of overall performance as compared to other existing routing protocols for Wireless Sensor Networks.

MANUFACTURING OF ENERGY EFFICIENT SOLAR PANELS

2020 ◽  
Author(s):  
Андрей Дмитриевич Бухтеев ◽  
Виктория Буянтуевна Бальжиева ◽  
Анна Романовна Тарасова ◽  
Фидан Гасанова ◽  
Светлана Викторовна Агасиева
Keyword(s):  
Energy Efficiency ◽  
Solar Cells ◽  
Energy Efficient ◽  
Solar Panels

В данном обзоре приведены проблемы при использовании солнечных элементов и существующие решения этих проблем по повышению энергоэффективности фотоэлементов. Также сравнивается КПД этих солнечных элементов и рассматриваются их особенности. Одним из самых эффективных способов стало применение нанотехнологий. This review presents the problems of using solar cells and existing solutions to these problems to improve the energy efficiency of solar cells. The efficiency of these solar cells is also compared and their features are considered. One of the most effective methods was the use of nanotechnology.

Energy efficient biomorphic pulse information coding in electronic neurons for the entrance unit of the neuroprocessor

2019 ◽  
Vol 5 (3) ◽  
pp. 186-212 ◽  
Author(s):  
Alexander D. Pisarev
Keyword(s):  
Neural Networks ◽  
Energy Efficiency ◽  
Energy Efficient ◽  
Information Transfer ◽  
Biological Systems ◽  
Technological Parameters ◽  
Input Unit ◽  
Efficient Operation ◽  
Electric Circuits ◽  
Electronic Neuron

This article studies the implementation of some well-known principles of information work of biological systems in the input unit of the neuroprocessor, including spike coding of information used in models of neural networks of the latest generation.<br> The development of modern neural network IT gives rise to a number of urgent tasks at the junction of several scientific disciplines. One of them is to create a hardware platform&nbsp;— a neuroprocessor for energy-efficient operation of neural networks. Recently, the development of nanotechnology of the main units of the neuroprocessor relies on combined memristor super-large logical and storage matrices. The matrix topology is built on the principle of maximum integration of programmable links between nodes. This article describes a method for implementing biomorphic neural functionality based on programmable links of a highly integrated 3D logic matrix.<br> This paper focuses on the problem of achieving energy efficiency of the hardware used to model neural networks. The main part analyzes the known facts of the principles of information transfer and processing in biological systems from the point of view of their implementation in the input unit of the neuroprocessor. The author deals with the scheme of an electronic neuron implemented based on elements of a 3D logical matrix. A pulsed method of encoding input information is presented, which most realistically reflects the principle of operation of a sensory biological neural system. The model of an electronic neuron for selecting ranges of technological parameters in a real 3D logic matrix scheme is analyzed. The implementation of disjunctively normal forms is shown, using the logic function in the input unit of a neuroprocessor as an example. The results of modeling fragments of electric circuits with memristors of a 3D logical matrix in programming mode are presented.<br> The author concludes that biomorphic pulse coding of standard digital signals allows achieving a high degree of energy efficiency of the logic elements of the neuroprocessor by reducing the number of valve operations. Energy efficiency makes it possible to overcome the thermal limitation of the scalable technology of three-dimensional layout of elements in memristor crossbars.

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