A heuristic mapping approach for wormhole switching based Network-on-Chip

2009 ◽  
Author(s):  
Yafei Cao ◽  
Dawei Wang ◽  
Sikun Li
Keyword(s):  
Network On Chip ◽  
Wormhole Switching ◽  
Mapping Approach ◽  
On Chip

scholarly journals A Self-Adaptive Mapping Approach for Network on Chip With Low Power Consumption

IEEE Access ◽  
2019 ◽  
Vol 7 ◽  
pp. 84066-84081 ◽  
Author(s):  
Aravindhan Alagarsamy ◽  
Lakshminarayanan Gopalakrishnan ◽  
Sundarakannan Mahilmaran ◽  
Seok-Bum Ko
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Network On Chip ◽  
Low Power Consumption ◽  
Mapping Approach ◽  
On Chip ◽  
Self Adaptive

Design of a high speed router for NOC

2021 ◽  
pp. 2140012
Author(s):  
Zhanpeng Jiang ◽  
Zhe Yang ◽  
Penghui Zhang ◽  
Changchun Dong
Keyword(s):  
High Speed ◽  
Control Mechanism ◽  
Network On Chip ◽  
Routing Algorithms ◽  
Performance Parameters ◽  
Wormhole Switching ◽  
Deterministic Routing ◽  
On Chip ◽  
Selection Of ◽  
Significant Point

The complexity of System on Chip (SoC) is increasing with the scale of ICs, and Network on Chip (NoC) has become one of the most important solutions for SoC communication. As a significant point of NoC, research of routers and routing algorithms is receiving more and more attention from researchers and research institutes. This paper proposes a high-speed router on-chip router, which adopts wormhole switching mechanism, output queuing caching strategy, Credit-based flow control mechanism and Round-Robin arbitration mechanism, and the entire operation of the router is a two-stage flow. The selection of adaptive and deterministic routing algorithms can be done automatically, and finally, the performance parameters are evaluated.

scholarly journals MSP based thermal-aware mapping approach for 3D Network-on-Chip under performance constraints

2016 ◽  
Vol 13 (7) ◽  
pp. 20160082-20160082 ◽  
Author(s):  
Gui Feng ◽  
Fen Ge ◽  
Ning Wu ◽  
Lei Zhou ◽  
Jing Liu
Keyword(s):  
Network On Chip ◽  
Performance Constraints ◽  
Mapping Approach ◽  
3D Network ◽  
On Chip

Pre-allocated Path Based Low Latency Router Architecture for Network-on-chip

2014 ◽  
Vol 35 (2) ◽  
pp. 341-346
Author(s):  
Xiao-fu Zheng ◽  
Hua-xi Gu ◽  
Yin-tang Yang ◽  
Zhong-fan Huang
Keyword(s):  
Network On Chip ◽  
Low Latency ◽  
Router Architecture ◽  
On Chip
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