Effects of manganese oxide–mixed abrasive slurry on the tetraethyl orthosilicate oxide chemical mechanical polishing for planarization of interlayer dielectric film in the multilevel interconnection

ABSTRACTThis paper addresses an important process issue in tie integration of chemical mechanical polishing (CMP) with interlayer dielectric (ILD) deposition for advanced back end processing. Gap fill between metal lines is achieved by using a dep-etch-dep technique for the tetraethylorthosilicate (TEOS) ILD deposition. The ILD layer is then planarized by CMP. Vias are etched through the ILD and filled with tungsten plugs in a blanket tungsten deposition and tungsten CMP sequence. Delamination has been observed at the interface between the TEOS layers following the blanket tungsten deposition and before or during tungsten CMP. The weak interface between the TEOS layers was found to be the result of residual carbon and fluorine from the tetraflouromethane (CF4) doped etch process. The interface between the TEOS layers was examined using X-ray photoelectron spectroscopy (XPS) and atomic force microscopy (AFM). Experiments were carried out to determine if the residue and subsequent delamination could be eliminated by modifying the dep-etch-dep process. An improved process was identified and has been implemented on a 0.5μm CMOS and mixed-mode BiCMOS production line with no subsequent occurrence of interfacial delamination.

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Investigations Of The Chemical-Mechanical Polishing Of Polymer Films For ILD Applications

MRS Proceedings ◽

10.1557/proc-381-229 ◽

1995 ◽

Vol 381 ◽

Cited By ~ 4

Author(s):

Jan. M. Neirynck ◽

S. P. Murarka ◽

R. J. Gutmann

Keyword(s):

Dielectric Constant ◽

Chemical Mechanical Polishing ◽

Chemical Properties ◽

Mechanical Polishing ◽

Low Dielectric Constant ◽

Acidic Ph ◽

Interlayer Dielectric ◽

Low Dielectric ◽

Damascene Process ◽

And Chemical Properties

AbstractLow dielectric constant films are being investigated as the interlayer dielectric (ILD) in a multilevel interconnection scheme for advanced ULSI circuits. In such applications they will be subjected to planarization processes using chemical-mechanical polishing (CMP), either directly during dielectric planarization or indirectly in the final stages of metal patterning using the Damascene process. In this paper we report the results of our initial investigations of the CMP of three different polymers, all with dielectric constant in the range of 2.3 – 2.7 and with different mechanical and chemical properties. The CMP was carried out using alumina as the abrasive in basic and acidic pH slurries. The effect of preannealing the polymer on the CMP behavior was also investigated

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The Surface Damage in SiO2 Caused by Chemical Mechanical Polishing on Ic-60 Pads

MRS Proceedings ◽

10.1557/proc-337-157 ◽

1994 ◽

Vol 337 ◽

Cited By ~ 2

Author(s):

Shyam Murarka ◽

Sen-Hou Ko ◽

Minoru Tomozawa ◽

Pei-Jun Ding ◽

William A. Lanford

Keyword(s):

Electrical Properties ◽

Nuclear Reaction ◽

Chemical Mechanical Polishing ◽

Colloidal Silica ◽

Surface Damage ◽

Mechanical Polishing ◽

Interlayer Dielectric ◽

Silicon Devices ◽

Thermal Oxide ◽

Silica Slurry

ABSTRACTChemical Mechanical polishing (CMP) is a useful technique for achieving global planarization in the ICs. The CMP of oxide has been used and studied for decades. Only recently the technique has been employed for planarizing the interlayer dielectric (ILD) on the silicon devices circuits. The effect of such polishing on the performance of the ILD has been the concern. This paper examines the attempts on defining the damage caused by CMP and its effect on the electrical properties after polished SiO2 wafers. In this investigation the PECVD and thermal oxide films were polished in the colloidal silica slurry on IC 60 pad. The polished oxide were then studied using I-V and nuclear reaction technique. The results show a surface damage which extends to about 800 Å in the polished oxide. The changes occurring in the concentration of hydrogenous species at the surface of SiO2 as determined by nuclear reaction technique will also be presented. It is shown that due to CMP as-deposited CVD SiO2 films loose water from surface regions whereas well annealed or dry oxides gain water at the surface. The results will be discussed and mechanisms will be presented to explain electrical results.

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