The Evolution of Organosilicon Precursors for Low-k Interlayer Dielectric Fabrication Driven by Integration Challenges

Since the application of silicon materials in electronic devices in the 1950s, microprocessors are continuously getting smaller, faster, smarter, and larger in data storage capacity. One important factor that makes progress possible is decreasing the dielectric constant of the insulating layer within the integrated circuit (IC). Nevertheless, the evolution of interlayer dielectrics (ILDs) is not driven by a single factor. At first, the objective was to reduce the dielectric constant (k). Reduction of the dielectric constant of a material can be accomplished by selecting chemical bonds with low polarizability and introducing porosity. Moving from silicon dioxide, silsesquioxane-based materials, and silica-based materials to porous silica materials, the industry has been able to reduce the ILDs’ dielectric constant from 4.5 to as low as 1.5. However, porous ILDs are mechanically weak, thermally unstable, and poorly compatible with other materials, which gives them the tendency to absorb chemicals, moisture, etc. All these features create many challenges for the integration of IC during the dual-damascene process, with plasma-induced damage (PID) being the most devastating one. Since the discovery of porous materials, the industry has shifted its focus from decreasing ILDs’ dielectric constant to overcoming these integration challenges. More supplementary precursors (such as Si-C-Si structured compounds), deposition processes (such as NH3 plasma treatment), and post porosity plasma protection treatment (P4) were invented to solve integration-related challenges. Herein, we present the evolution of interlayer dielectric materials driven by the following three aspects, classification of dielectric materials, deposition methods, and key issues encountered and solved during the integration phase. We aim to provide a brief overview of the development of low-k dielectric materials over the past few decades.

A comparison of the Cu electrochemical migration behavior between Cu lines with 5 um L/S realized by conventional Semi Additive Process (SAP) and an innovative Excimer Laser Damascene Process

The technological evolution regarding multi-chip integrated Fan-Out packages and chip scale packages (CSPs) with high amounts of I/O demands for even higher routing densities. Conventional used technologies and materials like mask aligner and photosensitive polymers used for semi additive process (SAP) in the BEOL have reached its limits to push the resolution down to two um. New materials and technologies are necessary to overcome these limits. As the routing density increases, so does the reliability requirements. The electrochemical migration between Cu lines cannot be neglected and need to be analyzed as the distance between the Cu lines is decreasing. A new approach for fine-line multi redistribution layers (RDL) realized by an excimer laser dual damascene process was presented in the past, using laser ablation and Cu chemical mechanical planarization (CMP) to realize embedded Cu lines. This approach has several advantages regarding the processing but one of the most important characteristics of the damascene approach is the improved electrochemical migration behavior. The Cu lines are partially cladded by the Ti part of the seed layer due to the way of processing. The Ti acts as a barrier layer and inhibits the Cu migration into the surrounding polymer. RDL structures realized by conventional SAP have Ti only under and not between the Cu lines. In this study different test samples with interdigital structures (resp. interdigital capacitor IDC) with five um line and space width (L/S) were realized to analyze the electrochemical migration behavior between the fingers of the IDC. The samples were realized by SAP and by the excimer laser damascene process and were subsequently tested by the temperature humidity bias (THB) test resp. biased High Accelerated Stress Test (bHAST). With the help of this work, we were able to compare the reliability of both process variants and to demonstrate and prove the reliability of embedded copper lines realized by the excimer laser damascene process.