System-on-chip field-programmable gate array design for onboard real-time hyperspectral unmixing

2016 ◽  
Vol 10 (1) ◽  
pp. 015004 ◽  
Author(s):  
José M. P. Nascimento ◽  
Mário Véstias
Keyword(s):  
Real Time ◽  
Field Programmable Gate Array ◽  
System On Chip ◽  
Array Design ◽  
Hyperspectral Unmixing ◽  
Field Programmable ◽  
Gate Array ◽  
On Chip

Real-time implementation of an auditory nerve model using a system-on-chip field-programmable gate array

2020 ◽  
Vol 148 (4) ◽  
pp. 2468-2468
Author(s):  
Matthew Blunt ◽  
Hezekiah Austin ◽  
Trevor Vannoy ◽  
Tyler Davis ◽  
Ross Snider
Keyword(s):  
Real Time ◽  
Auditory Nerve ◽  
Field Programmable Gate Array ◽  
System On Chip ◽  
Field Programmable ◽  
Nerve Model ◽  
Gate Array ◽  
On Chip

scholarly journals Remote TSN Frame Encapsulation by means of FPGA

2021 ◽  
Author(s):  
Jaime Jiménez ◽  
Igor Rodríguez ◽  
David Reguilón ◽  
Aitzol Zuloaga ◽  
Jesús Lázaro
Keyword(s):  
Real Time ◽  
Field Programmable Gate Array ◽  
Industry 4.0 ◽  
Frame Analysis ◽  
System On Chip ◽  
The Other ◽  
Ideal Solution ◽  
Field Programmable ◽  
Real Time Transmission ◽  
On Chip

Abstract TSN (Time-Sensitive Networking) has replaced outdated Fieldbus and non-deterministic Ethernet in the Industry 4.0. Field buses are not capable of providing neither connection for industry 4.0 IoT (Internet of Things) nor compatibility between different manufacturers. On the other hand, Ethernet is not able to ensure real-time. On the contrary, TSN guarantees real-time transmission, IoT and compatibility between devices. However, adapting to frequently changing needs makes TSN protocol evolve continuously. For this reason, devices for TSN analysis, such as PCs or not advanced frame analysis equipment are not able to process TSN packets at the speed that standard advances, discarding them as wrong frames. The integration of a System on Chip (SoC) that contains an FPGA (Field Programmable Gate Array) and a microcontroller, with capacity for reconfiguration and monitoring of the frames in the protocol, would be an ideal solution to this problem. This paper describes how to encapsulate TSN frames in Ethernet packets using an FPGA. Such Ethernet frames can subsequently be decapsulated, i.e. in a PC, and thus enable analysing TSN traffic in nonspecialized devices.

Implementing the open master hearing aid on a system-on-chip field programmable gate array

2020 ◽  
Vol 148 (4) ◽  
pp. 2508-2508
Author(s):  
Ross Snider ◽  
Matthew Blunt ◽  
Trevor Vannoy ◽  
Dustin Sobrero ◽  
Dylan Wickham ◽  
...  
Keyword(s):  
Field Programmable Gate Array ◽  
Hearing Aid ◽  
System On Chip ◽  
Field Programmable ◽  
Gate Array ◽  
On Chip
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