Index-Shuffle Graphs

1997 ◽  
Vol 08 (03) ◽  
pp. 289-304 ◽  
Author(s):  
Marc Baumslag ◽  
Bojana Obrenić
Keyword(s):  
Interconnection Networks ◽  
Graph Embedding ◽  
Theoretical Framework ◽  
Parallel Computers ◽  
Bounded Degree ◽  
Exchange Graph ◽  
Comparative Advantages ◽  
On Line

Index-shuffle graphs are introduced as candidate interconnection networks for parallel computers. The comparative advantages of index-shuffle graphs over the standard bounded-degree "approximations" of the hypercube, namely butterfly-like and shuffle-like graphs, are demonstrated in the theoretical framework of graph embedding and network emulations. An N-node index-shuffle graph emulates: • an N-node shuffle-exchange graph with no slowdown, which the currently best emulations of shuffle-like graphs by hypercubes and butterflies incur a slowdown of Ω( log N). • its like-sized butterfly graph with a slowdown O( log log log N), while the currently best emulations of butterfly-like graphs by shuffle-like graphs incur a slowdown of Ω( log log N). • an N-node hypercube that executes an on-line leveled algorithm with a slowdown O( log log N), while the slowdown of currently best such emulations of the hypercube by its bounded-degree shuffle-like and butterfly-like derivatives remains Ω( log N). Our emulation is based on an embedding of an N-node hypercube into an N-node index-shuffle graph with dilation O( log log N), while the currently best embeddings of the hypercube into its bounded-degree shuffle-like and butterfly-like derivatives incur a dilation of Ω( log N).

APPROXIMATING HYPERCUBES BY INDEX-SHUFFLE GRAPHS VIA DIRECT-PRODUCT EMULATIONS

2004 ◽  
Vol 05 (04) ◽  
pp. 429-473
Author(s):  
BOJANA OBRENIĆ
Keyword(s):  
Direct Product ◽  
Binary Tree ◽  
Interconnection Networks ◽  
Graph Embedding ◽  
Theoretical Framework ◽  
Parallel Computers ◽  
Complete Binary Tree ◽  
Bounded Degree ◽  
Graph Families ◽  
Unique Potential

Index-shuffle graphs are a family of bounded-degree hypercube-like interconnection networks for parallel computers, introduced by [Baumslag and Obrenić (1997): Index-Shuffle Graphs, …], as an efficient substitute for two standard families of hypercube derivatives: butterflies and shuffle-exchange graphs. In the theoretical framework of graph embedding and network emulations, this paper shows that the index-shuffle graph efficiently approximates the direct-product structure of the hypercube, and thereby has a unique potential to approximate efficiently all of its derivatives. One of the consequences of our results is that any member of the following group of standard bounded-degree hypercube derivatives: butterflies, shuffles, tori, meshes of trees, is emulated by the index-shuffle graph with a slowdown in the order of the logarithm of the slowdown of the most efficient emulation achieved by any other member of this group. Emulation algorithms are presented where the emulation host is the n-dimensional index-shuffle graph Ψn, having N=2n nodes. The emulated graph G is a direct product of the form: G=F0×F1×⋯×Fk-1 where k is a power of 2, and each factor Fi is an instance of any of the following three graph families: cycle, complete binary tree, X-tree. Let the size of each factor be |Fi|≤2nf, where k·nf≤n. The index-shuffle graph Ψn, emulates any factor Fi in the product G with slowdown: O( log k) + O( log nf), which is O( log n) = O( log log N). Any collection of 2ℓ copies of the product G, such that: ℓ+k·nf≤n is emulated by the index-shuffle graph Ψn simultaneously, without any additional slowdown. Relaxing the assumption that k is a power of 2 introduces an additional factor of O( lg *N) into the slowdown.

THE CUBE-OF-RINGS INTERCONNECTION NETWORK

1998 ◽  
Vol 09 (01) ◽  
pp. 25-37 ◽  
Author(s):  
THOMAS J. CORTINA ◽  
ZHIWEI XU
Keyword(s):  
Graph Theory ◽  
Interconnection Networks ◽  
Fault Tolerant ◽  
Interconnection Network ◽  
Routing Algorithm ◽  
Parallel Computers ◽  
Closed Form Expression ◽  
Form Expression ◽  
Graph Theoretic ◽  
Basic Graph

We present a family of interconnection networks named the Cube-Of-Rings (COR) networks along with their basic graph-theoretic properties. Aspects of group graph theory are used to show the COR networks are symmetric and optimally fault tolerant. We present a closed-form expression of the diameter and optimal one-to-one routing algorithm for any member of the COR family. We also discuss the suitability of the COR networks as the interconnection network of scalable parallel computers.

On-Line Process Control Compositional Analysis of Aluminum Films Containing a Low Percentage of Copper

1971 ◽  
Vol 15 ◽  
pp. 539-547
Author(s):  
G. H. Glade ◽  
J. M. Matthews ◽  
F. R. Titcomb
Keyword(s):  
Process Control ◽  
Interconnection Networks ◽  
Semiconductor Device ◽  
Compositional Analysis ◽  
Aluminum Film ◽  
Portable Instrument ◽  
Aluminum Films ◽  
On Line ◽  
Line Process ◽  
Control Application

Aluminum film conducting stripes are widely used for semiconductor device interconnection networks. The addition of a low percentage of copper significantly increases their life. Composition must be controlled to maintain product quality.The paper discusses various methods used to analyze the copper composition in the aluminum films, and adaptation of one of these methods for process control application. A portable instrument designed for field use was adapted for use as an on-line instrument.

FACILITATING HIGH-PERFORMANCE IMAGE ANALYSIS ON REDUCED HYPERCUBE (RH) PARALLEL COMPUTERS

1995 ◽  
Vol 09 (04) ◽  
pp. 679-698 ◽  
Author(s):  
SOTIRIOS G. ZIAVRAS ◽  
MICHALIS A. SIDERAS
Keyword(s):  
Image Analysis ◽  
Interconnection Networks ◽  
High Performance ◽  
Interconnection Network ◽  
Parallel Computers ◽  
Number Of Publications ◽  
Low Dimensional ◽  
High Level ◽  
The Cost ◽  
Cube Connected Cycles

The direct binary hypercube interconnection network has been very popular for the design of parallel computers, because it provides a low diameter and can emulate efficiently the majority of the topologies frequently employed in the development of algorithms. The last fifteen years have seen major efforts to develop image analysis algorithms for hypercube-based parallel computers. The results of these efforts have culminated in a large number of publications included in prestigious scholarly journals and conference proceedings. Nevertheless, the aforementioned powerful properties of the hypercube come at the cost of high VLSI complexity due to the increase in the number of communication ports and channels per PE (processing element) with an increase in the total number of PE’s. The high VLSI complexity of hypercube systems is undoubtedly their dominant drawback; it results in the construction of systems that contain either a large number of primitive PE’s or a small number of powerful PE’s. Therefore, low-dimensional k-ary n-cubes with lower VSLI complexity have recently drawn the attention of many designers of parallel computers. Alternative solutions reduce the hypercube’s VLSI complexity without jeopardizing its performance. Such an effort by Ziavras has resulted in the introduction of reduced hypercubes (RH’s). Taking advantage of existing high-performance routing techniques, such as wormhole routing, an RH is obtained by a uniform reduction in the number of edges for each hypercube node. An RH can also be viewed as several connected copies of the well-known cube-connected-cycles network. The objective here is to prove that parallel computers comprising RH interconnection networks are definitely good choices for all levels of image analysis. Since the exact requirements of high-level image analysis are difficult to identify, but it is believed that versatile interconnection networks, such as the hypercube, are suitable for relevant tasks, we investigate the problem of emulating hypercubes on RH’s. The ring (or linear array), the torus (or mesh), and the binary tree are the most frequently used topologies for the development of algorithms in low-level and intermediate-level image analysis. Thus, to prove the viability of the RH for the two lower levels of image analysis, we introduce techniques for embedding the aforementioned three topologies into RH’s. The results prove the suitability of RH’s for all levels of image analysis.

Layout of Embedding Circulant Networks into Linear Hexagons and Phenylenes

2013 ◽  
Vol 14 (03) ◽  
pp. 1350010
Author(s):  
INDRA RAJASINGH ◽  
MICHEAL AROCKIARAJ
Keyword(s):  
Interconnection Networks ◽  
Vlsi Design ◽  
Graph Embedding ◽  
Chemical Compounds ◽  
Theoretical Chemistry ◽  
Telecommunication Networks ◽  
Benzenoid Hydrocarbons ◽  
Graph Representations ◽  
Host Graph ◽  
Circulant Networks

Circulant network has been used for decades in the design of computer and telecommunication networks due to optimal fault-tolerance and routing capabilities. Further, it has been used in VLSI design and distributed computation. Hexagonal chains are of great importance of theoretical chemistry because they are the natural graph representations of benzenoid hydrocarbons, a great deal of investigations in mathematical chemistry has been developed to hexagonal chains. Hexagonal chains are exclusively constructed by hexagons of length one. Phenylenes are a class of chemical compounds in which carbon atoms form 6 and 4 membered cycles. Graph embedding has been known as a powerful tool for implementation of parallel algorithms or simulation of different interconnection networks. An embedding f of a guest graph G into a host graph H is a bijection on the vertices such that each edge of G is mapped into a path of H. The wirelength (layout) of this embedding is defined to be the sum of the length of the paths corresponding to the edges of G. In this paper we obtain the minimum wirelength of embedding circulant networks into linear hexagonal chains and linear phenylenes. Further we discuss the embedding of faulty circulant networks into linear hexagonal chains and linear phenylenes.

scholarly journals A New Record of Graph Enumeration Enabled by Parallel Processing

Mathematics ◽  
2019 ◽  
Vol 7 (12) ◽  
pp. 1214 ◽  
Author(s):  
Zhipeng Xu ◽  
Xiaolong Huang ◽  
Fabian Jimenez ◽  
Yuefan Deng
Keyword(s):  
Parallel Processing ◽  
Shortest Path ◽  
Interconnection Networks ◽  
New Record ◽  
Parallel Computers ◽  
Regular Graphs ◽  
Integer Sequences ◽  
Path Lengths ◽  
Online Encyclopedia ◽  
Processor Cores

Using three supercomputers, we broke a record set in 2011, in the enumeration of non-isomorphic regular graphs by expanding the sequence of A006820 in the Online Encyclopedia of Integer Sequences (OEIS), to achieve the number for 4-regular graphs of order 23 as 429,668,180,677,439, while discovering several regular graphs with minimum average shortest path lengths (ASPL) that can be used as interconnection networks for parallel computers. The enumeration of 4-regular graphs and the discovery of minimal-ASPL graphs are extremely time consuming. We accomplish them by adapting GENREG, a classical regular graph generator, to three supercomputers with thousands of processor cores.

Communication Issues in Parallel Systems with Optical Interconnections

1997 ◽  
Vol 08 (02) ◽  
pp. 143-162 ◽  
Author(s):  
Pascal Berthomé ◽  
Afonso Ferreira
Keyword(s):  
Interconnection Networks ◽  
Parallel Computers ◽  
Parallel Architectures ◽  
Massively Parallel ◽  
Optical Interconnections ◽  
Processing Elements ◽  
Bounded Number ◽  
Massively Parallel Computers ◽  
Communication Problems ◽  
Communication Operations

In classical massively parallel computers, the complexity of the interconnection networks is much higher than the complexity of the processing elements themselves. However, emerging optical technologies may provide a way to reconsider very large parallel architectures where processors would communicate by optical means. In this paper, we compare some optically interconnected parallel multicomputer models with regard to their communication capabilities. We first establish a distinction of such systems, based on the independence of the communication elements embedded in the processors (transmitters and receivers). Then, motivated by the fact that in multicomputers some communication operations have to be very efficiently performed, we study communication problems, namely, broadcast and multi-broadcast, under the hypothesis of bounded fanout. Our results take also into account a bounded number of available wavelengths.

A NEW FAMILY OF EXTREMAL INTERCONNECTION NETWORKS

2001 ◽  
Vol 02 (04) ◽  
pp. 421-444
Author(s):  
AARON HARWOOD ◽  
HONG SHEN
Keyword(s):  
Average Cost ◽  
Interconnection Networks ◽  
Interconnection Network ◽  
Practical Importance ◽  
Average Diameter ◽  
Bounded Degree ◽  
New Family ◽  
Bisection Width ◽  
Cyclomatic Number ◽  
Extremal Properties

We extensively discuss a new interconnection network topology, denoted by ϒ(n,r). Firstly, the ϒ(n,2) network is shown to provide average cost 3 log 2 n while providing superior fault tolerance characteristics. It is defined over any natural number of nodes n using 2n-3 edges for an average degree of 4 and has diameter no greater than k=⌈ log 2n⌉ with average diameter as small as [Formula: see text]. The network is planar and has cyclomatic number n-2. For n=2t the unbounded maximum degree is 2 log 2 n-1 believed indicative of generally a maximum unbounded degree O( log 2n). The bisection width ranges from 3 when n=2t to t+1 when n=2t+1. Secondly, we provide the ϒ*(n,r) network of bounded degree 2r. For n=rt the ϒ*(n,r) network has asymptotically better average cost than the general deBruijn(r,t) network while also maintaining planarity and cyclomatic property of ϒ(n,2). The ϒ family exhibits unique extremal properties of both theoretical interest and practical importance.

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