A PARALLEL PROCESSING MODEL FOR REAL-TIME COMPUTER VISION-AIDED ROAD TRAFFIC MONITORING

1992 ◽  
Vol 02 (02n03) ◽  
pp. 257-264 ◽  
Author(s):  
A. T. ALI ◽  
E. L. DAGLESS

A transputer-based parallel processing paradjgm for real-time extraction of road traffic data from video images of roadway scenes is proposed. The model can monitor three lanes of motorway traffic in real-time by processing images from two windows associated with each lane. Parallel algorithms are distributed among a network of transputers to perform similar and/or different tasks concerning image data analysis and traffic data extraction. The model can be expanded to cover more lanes or duplicated to monitor a further multi-lane carriageway.

2014 ◽  
Vol 977 ◽  
pp. 511-514
Author(s):  
Li Ping Huo ◽  
Xia Xu ◽  
Wei Wei Yao

The purpose of data analysis is to compress the data extraction, given its simplicity general description. In this paper, the dynamic attack traffic data, trying to establish in the metropolitan traffic monitoring data, according to the abnormal test, hypothesis testing and other methods of attack traffic identification and reasonable analysis, we found the type of attack traffic and network data from a wide range of macro-and related features, in order to provide a basis for analytical methods and techniques of network security data.


Author(s):  
Jean Bacon ◽  
Andrei Iu. Bejan ◽  
Alastair R. Beresford ◽  
David Evans ◽  
Richard J. Gibbens ◽  
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2014 ◽  
Vol 945-949 ◽  
pp. 1739-1743
Author(s):  
Jiang Bo Chen ◽  
Yong Ming Qiao ◽  
Zhuo Wei Hou

In order to realize the large field or view digital video images into PAL format analog video output,this article introduce a real-time display system of large visual field in the basis of FPGA. Apply the EP2S30F672I4 chip of the StraixII series to be the core processing unit, which is from the Altera; and the CSC12M25BMP19 camera, from the Teli, to be the image data source, with 25 Hz of output frame rate and a resolution of 2048 x 2048 on images. The Cameralink interface is adopted to be the data transmission channel between the camera and interface card, which carries out the configuration of the camera, image data acquisition, caching, image reduction and PAL format conversion, and finally accomplishes the image real-time display.This paper discusses the FPGA implementation of double bilinear interpolation algorithm, including image data frames buffer, the vertical and horizontal interpolation. The experiments results show that our expects are achieved by the algorithm and the hardware implementation.


2011 ◽  
Vol 15 (5) ◽  
pp. 651-665 ◽  
Author(s):  
Aengus McCullough ◽  
Philip James ◽  
Stuart Barr

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