scholarly journals A Middleware Approach to Achieving Fault Tolerance of Kahn Process Networks on Networks on Chips

2011 ◽  
Vol 2011 ◽  
pp. 1-15 ◽  
Author(s):  
Onur Derin ◽  
Erkan Diken ◽  
Leandro Fiorin
Keyword(s):  
Fault Tolerance ◽  
Open Source ◽  
Execution Time ◽  
Initial Step ◽  
Network On Chip ◽  
Distributed Model ◽  
Total Execution Time ◽  
Process Networks ◽  
Kahn Process ◽  
On Chip

Kahn process networks (KPNs) is a distributed model of computation used for describing systems where streams of data are transformed by processes executing in sequence or parallel. Autonomous processes communicate through unbounded FIFO channels in absence of a global scheduler. In this work, we propose a task-aware middleware concept that allows adaptivity in KPN implemented over a Network on Chip (NoC). We also list our ideas on the development of a simulation platform as an initial step towards creating fault tolerance strategies for KPNs applications running on NoCs. In doing that, we extend our SACRE (Self-Adaptive Component Run Time Environment) framework by integrating it with an open source NoC simulator, Noxim. We evaluate the overhead that the middleware brings to the the total execution time and to the total amount of data transferred in the NoC. With this work, we also provide a methodology that can help in identifying the requirements and implementing fault tolerance and adaptivity support on real platforms.

CRITICAL-PATH DRIVEN ROUTERS FOR ON-CHIP NETWORKS

2010 ◽  
Vol 19 (07) ◽  
pp. 1543-1557
Author(s):  
WEI HU ◽  
TIANZHOU CHEN ◽  
QINGSONG SHI ◽  
SHA LIU
Keyword(s):  
Computer Architecture ◽  
Execution Time ◽  
Critical Path ◽  
Network On Chip ◽  
Test Case ◽  
Total Execution Time ◽  
Multithreaded Programming ◽  
Multithreaded Program ◽  
On Chip ◽  
Dominant Paradigm

Multithreaded programming has become the dominant paradigm in computer architecture, mainly in the form of multi-core processors. The performance bottleneck of a multithreaded program is its critical path, whose length is its total execution time. As the number of cores within a processor increases, Network-on-Chip (NoC) has been proposed as a promising approach for inter-core communication. In order to optimize the performance of a multithreaded program running on an NoC based multi-core platform, we design and implement the critical-path driven router, which prioritizes inter-thread communication on the critical path when routing packets. The experimental results show that the critical-path driven router improves the execution time of the test case by 14.8% compared to the ordinary router.

Research on Network-on-Chip Dynamic and Adaptive Algorithm and Choice Strategy

2014 ◽  
Vol 539 ◽  
pp. 296-302
Author(s):  
Dong Li
Keyword(s):  
Energy Consumption ◽  
Execution Time ◽  
Adaptive Algorithm ◽  
Network On Chip ◽  
Time Dimension ◽  
Choice Strategy ◽  
Bus Structure ◽  
On Chip ◽  
Mapping Scheme ◽  
Single Objective

With further increase of the number of on-chip device, the bus structure has not met the requirements. In order to make better communication between each part, the chip designers need to explore a new structure to solve the interconnection of on-chip device. The paper proposes a network-on-chip dynamic and adaptive algorithm which selects NoC platform with 2-dimension mesh as the carrier, incorporates communication energy consumption and delay into unified cost function and uses ant colony optimization to realize NOC map facing energy consumption and delay. The experiment indicates that compared with random map, single objective optimization can separately saves (30%~47 %) and ( 20%~39%) in communication energy consumption and execution time compared with random map, and joint objective optimization can further excavate the potential of time dimension in mapping scheme dominated by the energy.

scholarly journals Adaptivity Support for MPSoCs Based on Process Migration in Polyhedral Process Networks

VLSI Design ◽  
2012 ◽  
Vol 2012 ◽  
pp. 1-17 ◽  
Author(s):  
Emanuele Cannella ◽  
Onur Derin ◽  
Paolo Meloni ◽  
Giuseppe Tuveri ◽  
Todor Stefanov
Keyword(s):  
Real Life ◽  
Data Communication ◽  
Network On Chip ◽  
Process Migration ◽  
Model Of Computation ◽  
Process Networks ◽  
Time Migration ◽  
Migration Mechanism ◽  
Run Time ◽  
On Chip

System adaptivity is becoming an important feature of modern embedded multiprocessor systems. To achieve the goal of system adaptivity when executing Polyhedral Process Networks (PPNs) on a generic tiled Network-on-Chip (NoC) MPSoC platform, we propose an approach to enable the run-time migration of processes among the available platform resources. In our approach, process migration is allowed by a middleware layer which comprises two main components. The first component concerns the inter-tile data communication between processes. We develop and evaluate a number of different communication approaches which implement the semantics of the PPN model of computation on a generic NoC platform. The presented communication approaches do not depend on the mapping of processes and have been implemented on a Network-on-Chip multiprocessor platform prototyped on an FPGA. Their comparison in terms of the introduced overhead is presented in two case studies with different communication characteristics. The second middleware component allows the actual run-time migration of PPN processes. To this end, we propose and evaluate a process migration mechanism which leverages the PPN model of computation to guarantee a predictable and efficient migration procedure. The efficiency and applicability of the proposed migration mechanism is shown in a real-life case study.

Reliable Fault-Tolerance Routing Technique for Network-on-Chip Interconnect

2021 ◽  
pp. 767-775
Author(s):  
Jayshree ◽  
Gopalakrishnan Seetharaman ◽  
Debadatta Pati
Keyword(s):  
Fault Tolerance ◽  
Network On Chip ◽  
On Chip

Mechanisms to Provide Fault Tolerance to a Network-on-Chip

2017 ◽  
Vol 15 (6) ◽  
pp. 1034-1042 ◽  
Author(s):  
Thiago Felski Pereira ◽  
Douglas Rossi de Melo ◽  
Eduardo Augusto Bezerra ◽  
Cesar Albenes Zeferino
Keyword(s):  
Fault Tolerance ◽  
Network On Chip ◽  
On Chip
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