A NEW PLATFORM FOR THE IMPLEMENTATION OF REGULAR ITERATIVE ALGORITHMS INTO FPGAs

2011 ◽  
Vol 20 (06) ◽  
pp. 975-999
Author(s):  
STAVROS P. DOKOUZYANNIS ◽  
ARGIRIS P. MOKIOS
Keyword(s):  
Large Scale ◽  
New Technology ◽  
Iterative Algorithms ◽  
Computer Arithmetic ◽  
Design Tool ◽  
Systolic Arrays ◽  
Field Programmable ◽  
Large Scale Integration ◽  
Scale Integration ◽  
Vlsi Chips

The implementation of regular iterative algorithms (RIAs) in important scientific fields such as image processing, computer arithmetic, cryptography and their implementation in processor arrays architectures, has been extensively studied over the last three decades. Numerous design methodologies and tools have been proposed, mostly targeting custom very large scale integration (VLSI) chips. The advent of field-programmable gate arrays (FPGAs) has attracted many researchers to incorporate previously acquired knowledge and experience in designing VLSI chips, to this new technology. This paper addresses the issue of the implementation of regular algorithms into FPGAs and presents a novel design tool for the implementation of RIAs, formulated as dependence graphs (DGs), on systolic arrays. Furthermore, a platform scheme for the systolic arrays hardware realization is proposed.

scholarly journals Revisiting the High-Performance Reconfigurable Computing for Future Datacenters

2020 ◽  
Vol 12 (4) ◽  
pp. 64 ◽  
Author(s):  
Qaiser Ijaz ◽  
El-Bay Bourennane ◽  
Ali Kashif Bashir ◽  
Hira Asghar
Keyword(s):  
Reconfigurable Computing ◽  
High Performance ◽  
Large Scale ◽  
Open Problems ◽  
Communication Architecture ◽  
Field Programmable ◽  
Large Scale Integration ◽  
On Chip ◽  
Scale Integration ◽  
Standard Terms

Modern datacenters are reinforcing the computational power and energy efficiency by assimilating field programmable gate arrays (FPGAs). The sustainability of this large-scale integration depends on enabling multi-tenant FPGAs. This requisite amplifies the importance of communication architecture and virtualization method with the required features in order to meet the high-end objective. Consequently, in the last decade, academia and industry proposed several virtualization techniques and hardware architectures for addressing resource management, scheduling, adoptability, segregation, scalability, performance-overhead, availability, programmability, time-to-market, security, and mainly, multitenancy. This paper provides an extensive survey covering three important aspects—discussion on non-standard terms used in existing literature, network-on-chip evaluation choices as a mean to explore the communication architecture, and virtualization methods under latest classification. The purpose is to emphasize the importance of choosing appropriate communication architecture, virtualization technique and standard language to evolve the multi-tenant FPGAs in datacenters. None of the previous surveys encapsulated these aspects in one writing. Open problems are indicated for scientific community as well.

scholarly journals Gesture Recognition Using Neural Networks Based on HW/SW Cosimulation Platform

2013 ◽  
Vol 2013 ◽  
pp. 1-13 ◽  
Author(s):  
Priyanka Mekala ◽  
Jeffrey Fan ◽  
Wen-Cheng Lai ◽  
Ching-Wen Hsue
Keyword(s):  
American Sign Language ◽  
Gesture Recognition ◽  
Large Scale ◽  
Vlsi Design ◽  
Field Programmable ◽  
Large Scale Integration ◽  
Neural Network Algorithm ◽  
Hardware Description ◽  
And Performance ◽  
Scale Integration

Hardware/software (HW/SW) cosimulation integrates software simulation and hardware simulation simultaneously. Usually, HW/SW co-simulation platform is used to ease debugging and verification for very large-scale integration (VLSI) design. To accelerate the computation of the gesture recognition technique, an HW/SW implementation using field programmable gate array (FPGA) technology is presented in this paper. The major contributions of this work are: (1) a novel design of memory controller in the Verilog Hardware Description Language (Verilog HDL) to reduce memory consumption and load on the processor. (2) The testing part of the neural network algorithm is being hardwired to improve the speed and performance. The American Sign Language gesture recognition is chosen to verify the performance of the approach. Several experiments were carried out on four databases of the gestures (alphabet signs A to Z). (3) The major benefit of this design is that it takes only few milliseconds to recognize the hand gesture which makes it computationally more efficient.

Plant hormones, plant growth regulators

2014 ◽  
Vol 155 (26) ◽  
pp. 1011-1018 ◽  
Author(s):  
György Végvári ◽  
Edina Vidéki
Keyword(s):  
Nervous System ◽  
Growth And Development ◽  
Large Scale ◽  
Essential Role ◽  
Higher Plants ◽  
Structure And Function ◽  
Wide Sense ◽  
Large Scale Integration ◽  
Scale Integration ◽  
And Function

Plants seem to be rather defenceless, they are unable to do motion, have no nervous system or immune system unlike animals. Besides this, plants do have hormones, though these substances are produced not in glands. In view of their complexity they lagged behind animals, however, plant organisms show large scale integration in their structure and function. In higher plants, such as in animals, the intercellular communication is fulfilled through chemical messengers. These specific compounds in plants are called phytohormones, or in a wide sense, bioregulators. Even a small quantity of these endogenous organic compounds are able to regulate the operation, growth and development of higher plants, and keep the connection between cells, tissues and synergy beween organs. Since they do not have nervous and immume systems, phytohormones play essential role in plants’ life. Orv. Hetil., 2014, 155(26), 1011–1018.

Behavior Models of Voltage Differencing Inverting Buffered Amplifier and Applications in Circuit Analysis

2019 ◽  
Vol 12 (4) ◽  
pp. 298-303
Author(s):  
YongAn LI
Keyword(s):  
Large Scale ◽  
Vlsi Design ◽  
Circuit Analysis ◽  
Second Order ◽  
Very Large Scale Integration ◽  
Behavioral Models ◽  
Order Filter ◽  
Large Scale Integration ◽  
Scale Integration ◽  
Behavior Models

Background: The symbolic nodal analysis acts as a pivotal part of the very large scale integration (VLSI) design. Methods: In this work, based on the terminal relations for the pathological elements and the voltage differencing inverting buffered amplifier (VDIBA), twelve alternative pathological models for the VDIBA are presented. Moreover, the proposed models are applied to the VDIBA-based second-order filter and oscillator so as to simplify the circuit analysis. Results: The result shows that the behavioral models for the VDIBA are systematic, effective and powerful in the symbolic nodal circuit analysis.</P>

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