scholarly journals Gesture Recognition Using Neural Networks Based on HW/SW Cosimulation Platform

2013 ◽  
Vol 2013 ◽  
pp. 1-13 ◽  
Author(s):  
Priyanka Mekala ◽  
Jeffrey Fan ◽  
Wen-Cheng Lai ◽  
Ching-Wen Hsue
Keyword(s):  
American Sign Language ◽  
Gesture Recognition ◽  
Large Scale ◽  
Vlsi Design ◽  
Field Programmable ◽  
Large Scale Integration ◽  
Neural Network Algorithm ◽  
Hardware Description ◽  
And Performance ◽  
Scale Integration

Hardware/software (HW/SW) cosimulation integrates software simulation and hardware simulation simultaneously. Usually, HW/SW co-simulation platform is used to ease debugging and verification for very large-scale integration (VLSI) design. To accelerate the computation of the gesture recognition technique, an HW/SW implementation using field programmable gate array (FPGA) technology is presented in this paper. The major contributions of this work are: (1) a novel design of memory controller in the Verilog Hardware Description Language (Verilog HDL) to reduce memory consumption and load on the processor. (2) The testing part of the neural network algorithm is being hardwired to improve the speed and performance. The American Sign Language gesture recognition is chosen to verify the performance of the approach. Several experiments were carried out on four databases of the gestures (alphabet signs A to Z). (3) The major benefit of this design is that it takes only few milliseconds to recognize the hand gesture which makes it computationally more efficient.

The Integration on Electrical Control Systems Based on Optimized Method

2012 ◽  
Vol 490-495 ◽  
pp. 2604-2608
Author(s):  
Ai Rong Zhang
Keyword(s):  
Integrated Circuit ◽  
Large Scale ◽  
Vlsi Design ◽  
Hardware Architecture ◽  
Logic Device ◽  
Integrated Circuit Design ◽  
Large Scale Integration ◽  
Hardware Description ◽  
Description Languages ◽  
Scale Integration

Very large scale integration (VLSI) applications have improved control implementation performance. Indeed, an application specific integrated circuit (ASIC) solution can exploit efficiently specificities of the control algorithms that fixed hardware architecture cannot do. For example, parallel calculation cannot be included in a software solution based on sequential processing. In addition, ASIC can reduce wire and electromagnetic field interference by a fully system on a chip (SoC) integration. However, there are still two main drawbacks to an integrated circuit solution: design complexity and reuse difficulty. This is true even with programmable logic device (PLD) solutions. Conception aid developer (CAD) combined with hardware description languages (HDL) and VLSI design methodology have accelerated conception and reuse. Nevertheless, the main problem of integrated circuit design is to define the hardware architecture; this is particularly true for heterogeneous algorithm structures such as electrical controls.

Behavior Models of Voltage Differencing Inverting Buffered Amplifier and Applications in Circuit Analysis

2019 ◽  
Vol 12 (4) ◽  
pp. 298-303
Author(s):  
YongAn LI
Keyword(s):  
Large Scale ◽  
Vlsi Design ◽  
Circuit Analysis ◽  
Second Order ◽  
Very Large Scale Integration ◽  
Behavioral Models ◽  
Order Filter ◽  
Large Scale Integration ◽  
Scale Integration ◽  
Behavior Models

Background: The symbolic nodal analysis acts as a pivotal part of the very large scale integration (VLSI) design. Methods: In this work, based on the terminal relations for the pathological elements and the voltage differencing inverting buffered amplifier (VDIBA), twelve alternative pathological models for the VDIBA are presented. Moreover, the proposed models are applied to the VDIBA-based second-order filter and oscillator so as to simplify the circuit analysis. Results: The result shows that the behavioral models for the VDIBA are systematic, effective and powerful in the symbolic nodal circuit analysis.</P>

VLSI Implementation and Software Co-Simulation of Digital Image Watermarking with Increased Security

2020 ◽  
Vol 10 (4) ◽  
pp. 634-638
Author(s):  
Vardhana M. ◽  
Anil Kumar Bhat
Keyword(s):  
Communication Systems ◽  
High Speed ◽  
Large Scale ◽  
Image Watermarking ◽  
Intensity Level ◽  
Performance Parameters ◽  
Security Measures ◽  
Large Scale Integration ◽  
And Performance ◽  
Scale Integration

Background: Security is one of the fundamental and essential factors, which has to be addressed in the field of communication. Communication refers to the exchange of useful information between two or more nodes. Sometimes it is required to exchange some of the confidential information such as a company’s logo, which needs to be hidden from the third person. The data that is being exchanged between these nodes has to be kept confidential and secured from unintended users. The three fundamental components of security are confidentiality, integrity and authentication. The data that is being exchanged has to be confidential, and only the authorized party should have access to the information that is being exchanged. One of the key methods for securing the data is encryption. Objective: The main objective of this paper was to address the problem of data hiding and security in communication systems. There is a need for having hardware resources for having high speed data security and protection. Methods: In this paper, we implemented image watermarking using LSB technique to hide a secret image, and employed encryption using Advanced Encryption Standard, to enhance the security of the image. An image is a two dimensional signal, with each pixel value representing the intensity level. The secure transmission of the image along the channel is a challenging task, because of the reason that, any individual can access it, if no security measures are taken. Conclusion: An efficient method of digital watermarking has been implemented with increased security and performance parameters are presented. Results: In this paper, hardware realization of image watermarking/encryption and dewatermarking/ decryption is implemented using Very Large Scale Integration. The design is verified by means of co-simulation using MATLAB and Xilinx. The paper also presents the performance parameters of the design, with respect to speed, area and power.

scholarly journals A HARDWARE IMPLEMENTATION OF PUNGURED CONVOLUTIONAL CODES TO COMPLETE A VITERBI DECODER CORE

2005 ◽  
Vol 3 (02) ◽  
Author(s):  
E. Garda ◽  
M. Guzmán ◽  
D. Torres
Keyword(s):  
Large Scale ◽  
Convolutional Codes ◽  
Viterbi Decoder ◽  
Single Chip ◽  
Description Language ◽  
Large Scale Integration ◽  
Constraint Length ◽  
Hardware Description ◽  
Scale Integration ◽  
Convolutional Encoder

This paper presents a VLSI (Very Large Scale Integration) implementation of high punctured convolutional codes.We present a new circuit architecture that is capable of processing up to 10 convolutional codes rate (n-1)/n withthe constraint length-7 derived by the puncturing technique from the basic rate-1/2. The present circuit wasdesigned in order to complete an existing Viterbi decoder core, adding some extra functionality such as aconvolutional encoder, differential encoder/decoder, punctured convolutional encoder and symbol insertion todepuncture the received data. This extra functionality includes 10 different programmable coding rates without theneed to add additional logic in the system implementation, while other existing coders need it to attain highercoding rates. Therefore, a single chip solution is presented. The design was implemented in VHDL (Very High SpeedIntegrated Circuit Hardware Description Language) synthesized in Synopsys tool, and tested in a FPGA. Functionalverification was done, by means of simulation, to ensure that the circuit implements intended functionality. Suchsimulations were executed using Synopsys and a Sun Ultra Sparc 10 workstation. Different bit error probabilityperformance curves show an agreement between simulated and theoretical values.

scholarly journals Rapid exploration of cost-performance tradeoffs using dominance effect during design of hardware accelerators

2014 ◽  
Vol 27 (3) ◽  
pp. 317-328 ◽  
Author(s):  
Reza Sedaghat ◽  
Anirban Sengupta
Keyword(s):  
Large Scale ◽  
Design Space Exploration ◽  
Hardware Accelerators ◽  
Cost Performance ◽  
Exploration Process ◽  
Final Design ◽  
Large Scale Integration ◽  
And Performance ◽  
Scale Integration ◽  
The Cost

Modern Very Large Scale Integration (VLSI) designs require a tradeoff between cost efficiency and performance (circuit speed). Furthermore, the Design Space Exploration (DSE) of the cost-performance tradeoffs for the multi objective VLSI designs should also be fast and efficient in nature. This paper presents a novel accelerated DSE approach for the exploration of cost-performance tradeoffs of modular multi (trio parametric. viz. cost, execution time and power consumption) objective VLSI hardware accelerators using hierarchical criterion analysis. The selection of the final design point is made after the tradeoffs are explored using the proposed approach. Results of the proposed approach when applied to various benchmarks yielded significant acceleration in the exploration process compared to current existing approaches with multi parametric objective.

Microstructures of Al(Pd, Nb) and Al(Ti) lines for VLSI

1992 ◽  
Vol 50 (2) ◽  
pp. 1388-1389
Author(s):  
C. Stanis ◽  
D. Smith ◽  
P. Blauner ◽  
M. Small
Keyword(s):  
Large Scale ◽  
Thermal Stresses ◽  
Feature Size ◽  
Silicon Devices ◽  
Large Scale Integration ◽  
Thermal Expansivities ◽  
Current Densities ◽  
And Performance ◽  
On Chip ◽  
Scale Integration

Very Large Scale Integration necessitated an ongoing and rapid decrease in the minimum feature size which must be made on silicon devices with the aims of improving productivity and performance. Conductor lines are commonly made from Al(Cu). Widths of 1.5 μm for conductor lines are common today, submicron lines are in late stages of development and 0.25 μm lines will be needed. These dimensions present new issues since the feature size is of the same order as the grain size of the Al and other metal alloys presently used for chip wiring. In order to make on-chip wiring reliable at these dimensions it is necessary to optimise the resistance to the stresses placed on them: electromigration due to increasing current densities; thermal stresses due to differences in thermal expansivities. The kinetics of both processes are dominated by interface transport. The resistance of the metal to both stresses can be modified by alloying.

A NEW PLATFORM FOR THE IMPLEMENTATION OF REGULAR ITERATIVE ALGORITHMS INTO FPGAs

2011 ◽  
Vol 20 (06) ◽  
pp. 975-999
Author(s):  
STAVROS P. DOKOUZYANNIS ◽  
ARGIRIS P. MOKIOS
Keyword(s):  
Large Scale ◽  
New Technology ◽  
Iterative Algorithms ◽  
Computer Arithmetic ◽  
Design Tool ◽  
Systolic Arrays ◽  
Field Programmable ◽  
Large Scale Integration ◽  
Scale Integration ◽  
Vlsi Chips

The implementation of regular iterative algorithms (RIAs) in important scientific fields such as image processing, computer arithmetic, cryptography and their implementation in processor arrays architectures, has been extensively studied over the last three decades. Numerous design methodologies and tools have been proposed, mostly targeting custom very large scale integration (VLSI) chips. The advent of field-programmable gate arrays (FPGAs) has attracted many researchers to incorporate previously acquired knowledge and experience in designing VLSI chips, to this new technology. This paper addresses the issue of the implementation of regular algorithms into FPGAs and presents a novel design tool for the implementation of RIAs, formulated as dependence graphs (DGs), on systolic arrays. Furthermore, a platform scheme for the systolic arrays hardware realization is proposed.

scholarly journals Revisiting the High-Performance Reconfigurable Computing for Future Datacenters

2020 ◽  
Vol 12 (4) ◽  
pp. 64 ◽  
Author(s):  
Qaiser Ijaz ◽  
El-Bay Bourennane ◽  
Ali Kashif Bashir ◽  
Hira Asghar
Keyword(s):  
Reconfigurable Computing ◽  
High Performance ◽  
Large Scale ◽  
Open Problems ◽  
Communication Architecture ◽  
Field Programmable ◽  
Large Scale Integration ◽  
On Chip ◽  
Scale Integration ◽  
Standard Terms

Modern datacenters are reinforcing the computational power and energy efficiency by assimilating field programmable gate arrays (FPGAs). The sustainability of this large-scale integration depends on enabling multi-tenant FPGAs. This requisite amplifies the importance of communication architecture and virtualization method with the required features in order to meet the high-end objective. Consequently, in the last decade, academia and industry proposed several virtualization techniques and hardware architectures for addressing resource management, scheduling, adoptability, segregation, scalability, performance-overhead, availability, programmability, time-to-market, security, and mainly, multitenancy. This paper provides an extensive survey covering three important aspects—discussion on non-standard terms used in existing literature, network-on-chip evaluation choices as a mean to explore the communication architecture, and virtualization methods under latest classification. The purpose is to emphasize the importance of choosing appropriate communication architecture, virtualization technique and standard language to evolve the multi-tenant FPGAs in datacenters. None of the previous surveys encapsulated these aspects in one writing. Open problems are indicated for scientific community as well.

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