Effectiveness of DFS Tuning on Java Server Workload

Dynamic frequency scaling (DFS) is a feature commonly found in modern processors. It lowers the clock frequency of a core according to the load level and reduces the power consumption. In this paper, we present a case study of tuning DFS parameters on a platform with an AMD Phenom II X6 using the SPECjEnterprise2010 (jEnt10) and SPECjbb2005 (jbb05) as the workload. In jEnt10, a longer sampling period of core utilization (up to 1.5[Formula: see text]s) reduced the power by 6[Formula: see text]Watt at 25% load level. At 50% load level, combining it with an increased threshold level (98%) to switch the clock frequency further reduced the power consumption by up to 10[Formula: see text]Watt. In jbb05, stretching the sampling period was only effective up to 0.5[Formula: see text]s. The maximum reduction was observed at around 60% load level. Raising the threshold level was not effective for jbb05.

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Case study: Effectiveness of dynamic frequency scaling on server workload

2014 International Symposium on Integrated Circuits (ISIC) ◽

10.1109/isicir.2014.7029572 ◽

2014 ◽

Author(s):

Hitoshi Oi

Keyword(s):

Frequency Scaling ◽

Dynamic Frequency Scaling ◽

Dynamic Frequency

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Reconfiguration Techniques for Self-X Power and Performance Management on Xilinx Virtex-II/Virtex-II-Pro FPGAs

International Journal of Reconfigurable Computing ◽

10.1155/2011/671546 ◽

2011 ◽

Vol 2011 ◽

pp. 1-12 ◽

Cited By ~ 3

Author(s):

Christian Schuck ◽

Bastian Haetzer ◽

Jürgen Becker

Keyword(s):

Performance Management ◽

High Speed ◽

Clock Frequency ◽

Frequency Scaling ◽

Clock Networks ◽

Digital Clock ◽

Dynamic Frequency Scaling ◽

Global Clock ◽

Clock Distribution Network ◽

Dynamic Frequency

Xilinx Virtex-II family FPGAs support an advanced low-skew clock distribution network with numerous global clock nets to support high-speed mixed frequency designs. Digital Clock Managers in combination with Global Clock Buffers are already in place to generate the desired frequency and to drive the clock networks with different sources, respectively. Currently, almost all designs run at a fixed clock frequency determined statically during design time. Such systems cannot take the full advantage of partial and dynamic self-reconfiguration. Therefore, we introduce a new methodology that allows the implemented hardware to dynamically self-adopt the clock frequency during runtime by reconfiguring the Digital Clock Managers. We also present a method for online speed monitoring which is based on a two-dimensional online routing. The created speed maps of the FPGA area can be used as an input for the dynamic frequency scaling. Figures for reconfiguration performance and power savings are given. Further, the tradeoffs for reconfiguration effort using this method are evaluated. Results show the high potential and importance of the distributed dynamic frequency scaling method with little additional overhead.

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