Mechanism of Threshold Voltage Shift (ΔVth) Caused by Negative Bias Temperature Instability (NBTI) in Deep Submicron pMOSFETs

2002 ◽  
Vol 41 (Part 1, No. 4B) ◽  
pp. 2423-2425 ◽  
Author(s):  
Chuan-Hsi Liu ◽  
Ming T. Lee ◽  
Chih-Yung Lin ◽  
Jenkon Chen ◽  
Y. T. Loh ◽  
...  
Keyword(s):  
Threshold Voltage ◽  
Deep Submicron ◽  
Negative Bias ◽  
Negative Bias Temperature Instability ◽  
Threshold Voltage Shift ◽  
Temperature Instability ◽  
Voltage Shift ◽  
Bias Temperature Instability

NEGATIVE BIAS TEMPERATURE INSTABILITY IN TIN/HF-SILICATE BASED GATE STACKS

2007 ◽  
Vol 17 (01) ◽  
pp. 129-141
Author(s):  
N. A. CHOWDHURY ◽  
D. MISRA ◽  
N. RAHIM
Keyword(s):  
Interface State ◽  
Initial Time ◽  
Negative Bias ◽  
Gate Stacks ◽  
Negative Bias Temperature Instability ◽  
Threshold Voltage Shift ◽  
Temperature Instability ◽  
Bias Temperature Instability ◽  
High Bias ◽  
The Impact

This work studies the effects of negative bias temperature instability (NBTI) on p-channel MOSFETS with TiN/HfSi x O y (20% SiO 2 based high-κ gate stacks under different gate bias and elevated temperature conditions. For low bias conditions, threshold voltage shift (ΔVT) is most probably due to the mixed degradation within the bulk high-κ. For moderately high bias conditions, H-species dissociation in the presence of holes and subsequent diffusion may be initially responsible for interface state and positively charged bulk trap generation. Initial time, temperature and oxide electric field dependence of ΔVT in our devices shows an excellent match with that of SiO 2 based devices, which is explained by reaction-diffusion (R-D) model of NBTI. Under high bias condition at elevated temperatures, due to higher Si - H bond-annealing/bond-breaking ratio, the experimentally observed absence of the impact ionization induced hot holes at the interfacial layer (IL)/ Si interface probably limits the interface state generation and ΔVT as they quickly reach saturation.

A Modified Architecture for Radix-4 Booth Multiplier with Adaptive Hold Logic

2016 ◽  
Vol 4 (1) ◽  
pp. 01-05
Author(s):  
S Suvarna ◽  
K Rajesh ◽  
T Radhu
Keyword(s):  
Threshold Voltage ◽  
High Speed ◽  
Negative Bias ◽  
Positive Bias ◽  
Negative Bias Temperature Instability ◽  
Discrete Cosine Transforms ◽  
Temperature Instability ◽  
Booth Multiplier ◽  
Bias Temperature Instability ◽  
Digital Multipliers

High speed digital multipliers are most efficiently used in many applications such as Fourier transform, discrete cosine transforms, and digital filtering. The throughput of the multipliers is based on speed of the multiplier, and then the entire performance of the circuit depends on it. The pMOS transistor in negative bias cause negative bias temperature instability (NBTI), which increases the threshold voltage of the transistor and reduces the multiplier speed. Similarly, the nMOS transistor in positive bias cause positive bias temperature instability (PBTI).These effects reduce the transistor speed and the system may fail due to timing violations. So here a new multiplier was designed with novel adaptive hold logic (AHL) using Radix-4 Modified Booth Multiplier. By using Radix-4 Modified Booth Encoding (MBE), we can reduce the number of partial products by half. Modified booth multiplier helps to provide higher throughput with low power consumption. This can adjust the AHL circuit to reduce the performance degradation. The expected result will be reduce threshold voltage, increase throughput and speed and also reduce power. This modified multiplier design is coded by Verilog and simulated using Xilinx ISE 12.1 and implemented in Spartan 3E FPGA kit.

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