Abstraction NBTI model

Negative Bias Temperature Instability (NBTI) is one of the major transistor aging effects, possibly leading to timing failures during run-time of a system. Thus one is interested in predicting this effect during design time. In this work an Abstraction NBTI model is introduced reducing the state space of trap-based NBTI models using two abstraction parameters, applying a state transformation to incorporate variable stress conditions. This transformation is faster than traditional approaches. Currently the conversion into estimated threshold voltage damages is a very time consuming process.

3.3V Transmitter Using 1.8V Transistors In A Cascode Configuration

A voltage-mode transmitter using a 1.8V-to-3.3V levelshifter and cascoded output buffer is proposed. 1.8V TSMC 65nm transistors are used. The design is targeted to meet JEDEC Interface Standard for Nominal 3 V/3.3 V Supply Digital Integrated Circuits DC Specifications as well as an AC transmission rate of 200 MHz on a 30 cm 50Ω board trace terminated with a 4 pF capacitive load. Overstress voltages will not be exceeded in order to avoid device failure due to breaching Gate Oxide Integrity, Hot Carrier Injection, or Negative Bias Temperature Instability.

3.3V Transmitter Using 1.8V Transistors In A Cascode Configuration

A voltage-mode transmitter using a 1.8V-to-3.3V levelshifter and cascoded output buffer is proposed. 1.8V TSMC 65nm transistors are used. The design is targeted to meet JEDEC Interface Standard for Nominal 3 V/3.3 V Supply Digital Integrated Circuits DC Specifications as well as an AC transmission rate of 200 MHz on a 30 cm 50Ω board trace terminated with a 4 pF capacitive load. Overstress voltages will not be exceeded in order to avoid device failure due to breaching Gate Oxide Integrity, Hot Carrier Injection, or Negative Bias Temperature Instability.