Packaging without the Package - A More Holistic Moore's Law

2017 ◽  
Vol 2017 (S1) ◽  
pp. 1-40
Author(s):  
Subramanian S. Iyer (Subu)
Keyword(s):  
System Integration ◽  
System Level ◽  
Heterogeneous Integration ◽  
Power Performance ◽  
Wafer Level ◽  
Innovative Materials ◽  
Barrier To Entry ◽  
On Chip ◽  
Market Consolidation ◽  
Conventional Systems

Silicon features have scaled by over 1500X for over six decades, and with the adoption of innovative materials delivered better power-performance, density and till recently, cost per function, almost every generation. This has spawned a vibrant system-on-chip (SoC) approach, where progressively more function has been integrated on a single die. The integration of multiple dies on packages and boards has, however, scaled only modestly by a factor of three to five times. However, as SoCs have become bigger and more complex, the Non-Recurring Engineering (NRE) Charge and time to market have both ballooned out of control leading to ever increasing market consolidation. We need to address this problem through novel methods of system Integration. With the well-documented slowing down of scaling and the advent of the Internet of Things, there is a focus on heterogeneous integration and system-level scaling. Packaging itself is undergoing a transformation that focuses on overall system performance through integration rather than on packaging individual components. We propose ways in which this transformation can evolve to provide a significant value at the system level while providing a significantly lower barrier to entry compared with a chip-based SoC approach that is currently used. More importantly it will allow us to re-architect systems in a very significant way. This transformation is already under way with 3-D stacking of dies, Wafer level fan-out processing, and will evolve to make heterogeneous integration the backbone of a new SoC methodology, extending to integrate entire Systems on Wafers (SoWs). We will describe the technology we use and the results to-date. This has implications in redefining the memory hierarchy in conventional systems and in neuromorphic systems. We extend these concepts to flexible and biocompatible electronics.

High-quality multiple global layers on chip-redistributed wafer for wafer-level system integration using pseudo-SOC

2011 ◽  
Vol 2011 (1) ◽  
pp. 000820-000827
Author(s):  
Atsuko IIDA ◽  
Yutaka ONOZUKA ◽  
Hiroshi YAMADA ◽  
Toshihiko NAGANO ◽  
Kazuhiko ITAYA
Keyword(s):  
Low Temperature ◽  
System Integration ◽  
Fem Simulation ◽  
High Sensitivity ◽  
High Accuracy ◽  
System Level ◽  
Level System ◽  
Wafer Level ◽  
High Quality ◽  
On Chip

This paper reports an advanced process to realize high-quality multiple global layers on high-accuracy chip-redistributed wafer for wafer-level system integration using pseudo-SOC. We have been developing pseudo-SOC (p-SOC) technology by which KGD chips are integrated to a chip-redistributed wafer using high-rigidity epoxy resin and global layers with interconnecting chips are formed on it. The basic process has been established for p-SOC, and integration of MEMS and LSI, or front-end RF LSI and passive components, has been demonstrated. However, the first stage of p-SOC technology was based on a single global layer consisting of an insulating layer and a conductive layer, which limited the range of application. It is desirable to realize high-quality multiple global layers on the high-accuracy chip-redistributed wafer in order to expand its application toward system-level integration. For this purpose, it is necessary to keep all processes at low temperature for the reduction of warpage in the resin-based chip-redistributed wafer during several resin curing processes, to readjust resin-based materials, and to obtain high accuracy of chip position in chip-redistributed wafer. We developed the advanced p-SOC process to resolve these technical issues by improving the hardening process of resin, employing low-temperature-curing polyimide and optimizing the stress analysis by FEM simulation. As a result, realization of a novel one-chip module for a versatile high-sensitivity amplifier is demonstrated.

3D RCP Package Stacking: Side Connect, An Emerging Technology for System Integration and Volumetric Efficiency

2013 ◽  
Vol 2013 (1) ◽  
pp. 000447-000451 ◽  
Author(s):  
Michael Vincent ◽  
Doug Mitchell ◽  
Jason Wright ◽  
Yap Weng Foong ◽  
Alan Magnus ◽  
...  
Keyword(s):  
System Integration ◽  
System Performance ◽  
Electrical Characterization ◽  
Emerging Technology ◽  
Volumetric Efficiency ◽  
Wafer Level ◽  
Novel Technologies ◽  
3D Packaging ◽  
Packaging Space ◽  
On Chip

Fan-out wafer level packaging (FO-WLP) has shifted from standard single die, single sided package to more advanced packages for System-in-Package (SiP) and 3D applications. Freescale's FO-WLP, Redistributed Chip Package (RCP), has enabled Freescale to create novel SiP solutions not possible in more traditional packaging technologies or Systems-on-Chip (SoC). Simple SiP's using two dimensional (2D), multi-die RCP solutions have resulted in significant package size reduction and improved system performance through shortened traces when compared to discretely packaged die or substrate based multi-chip module (MCM). More complex 3D SiP solutions allow for even greater volumetric efficiency of the packaging space. 3D RCP is a flexible approach to 3D packaging with complexity ranging from Package-on-Package (PoP) type solutions to systems including ten or more multi-sourced die with associated peripheral components. Perhaps the most significant SiP capability of the RCP technology is the opportunity for heterogeneous integration. The combination of various system elements including, but not limited to SMD's, CMOS, GaAs, MEMS, imaging sensors or IPD's gives system designers the capability to generate novel systems and solutions which can then enable new products for customers. To enable this ever increasing system integration and volumetric efficiency, novel technologies have been developed to utilize the full package space. Technologies such as through package via (TPV) and double sided redistribution are currently proving successful. For this discussion, an emerging technology for 3D RCP package stacking that can further enhance design flexibility and system performance is presented. This technology, package side connect, utilizes the vertical sides of packages and stacked packages to capture a normally unused piece of package real-estate. Mechanical and electrical characterization of successful side connects will be presented as well as reliability results of test vehicle packages using RCP packaging technology.

CoC (Chip on Chip) or FtoF (Face to Face) - PossumTM Technology for 3D MEMS and ASIC eliminating the need of TSV or Wire Bonding

2013 ◽  
Vol 2013 (DPC) ◽  
pp. 000916-000936
Author(s):  
Jemmy Sutanto ◽  
D. H. Kang ◽  
J. H. Yoon ◽  
K. S. Oh ◽  
Michael Oh ◽  
...  
Keyword(s):  
Form Factor ◽  
System Integration ◽  
Wire Bonding ◽  
Electrical Performance ◽  
Wafer Level ◽  
3D Integration ◽  
Face To Face ◽  
Parasitic Resistance ◽  
On Chip ◽  
Packaging Cost

This paper describes the ongoing 3 years research and development at Amkor Technology on CoC (Chip on Chip)/FtF (Face to Face) – PossumTM technology. This technology has showed a lot of interests from the microelectronics customers/industries because of its various advantages, which include a) providing smaller form factor (SFF) to the final package, b) more functionalities (dies) can be incorporated/assembled in one package, c) improving the electrical performance - including lower parasitic resistance, lower power, and higher frequency bandwidth, and d) Opportunity for lower cost 3D system integration. Unlike other 3D Packaging technology (e.g. using TSV (Through Silicon Vias)) that requires some works in the front stream (wafer foundry) level, needs new capitals for machines/equipments, and needs modified assembly lines; CoC/FtF technology uses the existing flip Chip Attach (C/A) or TC (Thermal Compression) equipment/machine to perform the assembly joint between the two dies, which are named as the mother (larger) die and the daughter (smaller) die. Furthermore, the cost to assemble CoC/FtF is relatively inexpensive while the applications are very wide and endless, which include the 3D integration of MEMS and ASIC. The current MEMS packaging and test cost contributes about 35 to 45% to the overall MEMS unit cost. WLC (Wafer Level Capping) with wire bonding have been widely used for mass production for accelerometer (e.g. ADI and Motorola), gyroscope (e.g. Bosch and Invensense), and oscillator /timer (e.g. Discera). The WLC produce drawbacks of a large form factor and the increase in the capacitive and electrical resistances. Currently, the industries have been developing a new approach of 3D WLP (Wafer Level Packaging) by using a) TSV MEMS cap with wire bonding (e.g. Discera), b) TSV MAME cap with solder bump (e.g. Samsung, IMEC, and VTI), and c) TSV MEMS wafer/die with cap (e.g. Silex Microsystems). The needs of TSVs in the 3D WLP will add the packaging cost and reduce the design flexibility is pre-TSV wafer is used. “Amkor CoC/FtoF – PossumTM” is an alternative technology for 3D integration of MEMS and ASIC. CoC/FtoF – PossumTM does not require TSV or wire bonding; Miniaturizing form factor of 1.5 mm x 1.5 mm x 0.95 mm (including the package) of MEMS and ASIC can be achieved by using CoC/FtoF – PossumTM while Discera's design of 3D WLP requires substrate size > 2 mm x 2 mm. CoC/FtoF – PossumTM will likely produce packaging cost which is lower than WLC or 3D WLP – TSV at the same time the customer is benefited from smaller FF and reduced electrical/parasitic resistance. CoC/FtoF – PossumTM can be applied to any substrates including FCBGA and laminate. This technology also can be applied to package multiple MEMS microsensors, together with ASIC, microcontroller, and wireless RF to realize the 3D system integration.

3D Process Integration – Requirements and Challenges

2008 ◽  
Vol 1112 ◽  
Author(s):  
Juergen Max Wolf ◽  
Armin Klumpp ◽  
Kai Zoschke ◽  
Robert Wieland ◽  
Lars Nebrich ◽  
...  
Keyword(s):  
System Integration ◽  
New Technologies ◽  
Process Integration ◽  
High Volume ◽  
System Level ◽  
Wafer Level ◽  
System Architectures ◽  
Future System ◽  
3D Packaging ◽  
Third Dimension

AbstractHeterogeneous system integration is one of the key topics for future system integration. Scaling of System on Chip (SoC) alone does not address today's requirements of smart electronic systems in terms of performance, functionality, miniaturization, low production cost and time to market. The traditional microelectronic packaging will more and more convert into complex sys-tem integration. ‘More than Moore’ will be required due to tighter integration of system level components at the package level. This trend leads to advanced System in Package solutions (SiP) which require the synergy and a combination of wafer level and board integration technologies and which are rapidly evolving from a specialty technology used in a narrow set of applications to a high volume technology with wide ranging impact on electronics markets especially due to the high volume and very cost competitive consumer and communication market. Advanced SiP approaches explore the third dimension which results in complex system architectures that also require, beside new technologies and improved materials, adequate system design tools and reli-ability models. One of the most promising technology approaches is 3D packaging which in-volves a set of different integration approaches including stacked packages, silicon interposer with Through Silicon Vias (TSV) and embedding technologies. The paper highlights future sys-tem and potential technical solutions.

Packaging and Integration Strategy for mm-Wave Products

2018 ◽  
Vol 2018 (1) ◽  
pp. 000252-000258 ◽  
Author(s):  
Urmi Ray ◽  
NJ Cho ◽  
YC Kim ◽  
SW Yoon ◽  
WK Choi ◽  
...  
Keyword(s):  
Form Factor ◽  
Antenna Arrays ◽  
System Integration ◽  
High Performance ◽  
Heat Dissipation ◽  
System Level ◽  
Wafer Level ◽  
Automotive Radar ◽  
Rf Transceiver ◽  
Trade Offs

Abstract This paper is a follow on to the paper presented at the IMAPS 14th International Conference DEVICE PACKAGING and will provide more comprehensive case studies of few different system integration strategies for high frequency packaging. The packaging options vary widely based on the end market requirements, from performance, thermal, types and numbers of antenna arrays as well as the RF transceiver ICs. Tied closely to these performance related requirements is competing trade-offs of reliability, form factor and cost. We present assessment of packaging structures for (a) high performance mm-Wave network product and (b) consumer/mobile product and (c) automotive radar product. The former (a) is generally not challenged by form factor and can be enhanced by the addition of more antenna arrays and RFICs. However, care has to be taken to address the thermal solutions for effective heat dissipation as well as manufacturability issues as the package size may target ~400mm2 for Gen 1 and double or triple the area for subsequent generations. For (b), the primary drivers are cost and form factor. To manage antenna propagation and losses in a constrained form factor, mobile products generally require antenna in package (AiP) integration. The integration of the antenna within the same package as the RF IC greatly reduces the difficulty at the system level. This approach coupled to aggressive miniaturization of the antenna itself, using the same substrate technologies as the SiP leads to a new class of sub-systems termed Antenna in Package (AiP). This is extremely challenging from design, manufacturability and test perspectives. For example, Fan out wafer level packaging, such as eWLB packaging provides extremely smooth copper surfaces with tight etch tolerance compared to standard laminate based packaging. However, having multiport antenna structures fabricated in fan out technology with inductance matching and efficient ground ports, continue to be problematic. Hence adoption of 3D structures, in conjunction with SIP integration (with inductors and IPDs) can potentially provide relief. Inductors can also be built into the eWLB structure using the RDL as well as in the laminate packages using substrate embedded thin film cores.

Assembly and Packaging Enabling System Integration

2013 ◽  
Vol 2013 (1) ◽  
pp. 000171-000176 ◽  
Author(s):  
Klaus Pressel ◽  
Gottfried Beer ◽  
Maciej Wojnowski
Keyword(s):  
Energy Efficiency ◽  
Silicon Wafer ◽  
System Integration ◽  
Ball Grid Array ◽  
Mobile Systems ◽  
Heterogeneous Integration ◽  
Wafer Level ◽  
Nanoelectronic Devices ◽  
Wafer Level Packaging ◽  
Major Trend

More than Moore is a major trend to tackle the increasing difficulties of traditional Moore's law scaling. System in Package technologies, which allow heterogeneous integration, are appearing in ever more electronic applications. Furthermore we observe merging of silicon wafer technology with assembly and packaging technologies. Today a more coherent development taking into account chip, package, and the board is needed. In this paper we show how assembly and packaging can take up the slack because traditional More Moore downscaling is becoming more difficult. First, we introduce the Thin Small Leadless Package (TSLP) e.g. used in mobile systems. The TSLP is similar to the Quad Flat No-Lead (QFN) package, but thinner and with less parasitics. Second, we introduce wafer level type packages. The limits of standard wafer level packaging in respect to I/O counts pushed the development of the embedded Wafer Level Ball Grid Array (eWLB). We demonstrate the outstanding system integration capabilities of the eWLB including excellent mm-wave performance. For all the above mentioned packages chip and package technologies merge. They are door opener for nanoelectronic devices in respect to energy efficiency, mobility and security.

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