A global interconnect link design for many-core microprocessors

Author(s):  
DiaaEldin Khalil ◽  
Yehea Ismail
2011 ◽  
Vol 470 ◽  
pp. 224-230
Author(s):  
Kazuya Masu ◽  
Shuhei Amakawa ◽  
Hiroyuki Ito ◽  
Noboru Ishihara

In the conventional scaling scheme, interconnect delay cannot be reduced and the global interconnect delay become worse if the length of the wire is not scaled. The conventional approaches of global interconnect design are (1)introduction of inverse scaling concept where the upper metal layers have larger cross sections than lower metal layers, (2)insertion of repeaters, and (3) architecture level approach of multi/many core. In order to improve global interconnect delay even in aggressively miniaturized circuit, we have developed the transmission lien interconnect. This paper describes the novel analytical interconnect length distribution and discussion on future interconnect design direction. Then, recent our developments of the transmission line interconnect are described and performance comparison with another global wiring scheme such as optical interconnection is discussed.


2014 ◽  
Vol E97.C (4) ◽  
pp. 360-368
Author(s):  
Takashi MIYAMORI ◽  
Hui XU ◽  
Hiroyuki USUI ◽  
Soichiro HOSODA ◽  
Toru SANO ◽  
...  
Keyword(s):  

2010 ◽  
Vol 33 (10) ◽  
pp. 1777-1787 ◽  
Author(s):  
Wei-Zhi XU ◽  
Feng-Long SONG ◽  
Zhi-Yong LIU ◽  
Dong-Rui FAN ◽  
Lei YU ◽  
...  
Keyword(s):  

2009 ◽  
Vol 31 (11) ◽  
pp. 1918-1928 ◽  
Author(s):  
Wei LIN ◽  
Xiao-Chun YE ◽  
Feng-Long SONG ◽  
Hao ZHANG
Keyword(s):  

Impact ◽  
2019 ◽  
Vol 2019 (10) ◽  
pp. 44-46
Author(s):  
Masato Edahiro ◽  
Masaki Gondo

The pace of technology's advancements is ever-increasing and intelligent systems, such as those found in robots and vehicles, have become larger and more complex. These intelligent systems have a heterogeneous structure, comprising a mixture of modules such as artificial intelligence (AI) and powertrain control modules that facilitate large-scale numerical calculation and real-time periodic processing functions. Information technology expert Professor Masato Edahiro, from the Graduate School of Informatics at the Nagoya University in Japan, explains that concurrent advances in semiconductor research have led to the miniaturisation of semiconductors, allowing a greater number of processors to be mounted on a single chip, increasing potential processing power. 'In addition to general-purpose processors such as CPUs, a mixture of multiple types of accelerators such as GPGPU and FPGA has evolved, producing a more complex and heterogeneous computer architecture,' he says. Edahiro and his partners have been working on the eMBP, a model-based parallelizer (MBP) that offers a mapping system as an efficient way of automatically generating parallel code for multi- and many-core systems. This ensures that once the hardware description is written, eMBP can bridge the gap between software and hardware to ensure that not only is an efficient ecosystem achieved for hardware vendors, but the need for different software vendors to adapt code for their particular platforms is also eliminated.


2018 ◽  
Vol 175 ◽  
pp. 02009
Author(s):  
Carleton DeTar ◽  
Steven Gottlieb ◽  
Ruizi Li ◽  
Doug Toussaint

With recent developments in parallel supercomputing architecture, many core, multi-core, and GPU processors are now commonplace, resulting in more levels of parallelism, memory hierarchy, and programming complexity. It has been necessary to adapt the MILC code to these new processors starting with NVIDIA GPUs, and more recently, the Intel Xeon Phi processors. We report on our efforts to port and optimize our code for the Intel Knights Landing architecture. We consider performance of the MILC code with MPI and OpenMP, and optimizations with QOPQDP and QPhiX. For the latter approach, we concentrate on the staggered conjugate gradient and gauge force. We also consider performance on recent NVIDIA GPUs using the QUDA library.


Author(s):  
Peter Benner ◽  
Ernesto Dufrechou ◽  
Pablo Ezzatti ◽  
Rodrigo Gallardo ◽  
Enrique S. Quintana-Ortí
Keyword(s):  

Micromachines ◽  
2021 ◽  
Vol 12 (2) ◽  
pp. 183
Author(s):  
Jose Ricardo Gomez-Rodriguez ◽  
Remberto Sandoval-Arechiga ◽  
Salvador Ibarra-Delgado ◽  
Viktor Ivan Rodriguez-Abdala ◽  
Jose Luis Vazquez-Avila ◽  
...  

Current computing platforms encourage the integration of thousands of processing cores, and their interconnections, into a single chip. Mobile smartphones, IoT, embedded devices, desktops, and data centers use Many-Core Systems-on-Chip (SoCs) to exploit their compute power and parallelism to meet the dynamic workload requirements. Networks-on-Chip (NoCs) lead to scalable connectivity for diverse applications with distinct traffic patterns and data dependencies. However, when the system executes various applications in traditional NoCs—optimized and fixed at synthesis time—the interconnection nonconformity with the different applications’ requirements generates limitations in the performance. In the literature, NoC designs embraced the Software-Defined Networking (SDN) strategy to evolve into an adaptable interconnection solution for future chips. However, the works surveyed implement a partial Software-Defined Network-on-Chip (SDNoC) approach, leaving aside the SDN layered architecture that brings interoperability in conventional networking. This paper explores the SDNoC literature and classifies it regarding the desired SDN features that each work presents. Then, we described the challenges and opportunities detected from the literature survey. Moreover, we explain the motivation for an SDNoC approach, and we expose both SDN and SDNoC concepts and architectures. We observe that works in the literature employed an uncomplete layered SDNoC approach. This fact creates various fertile areas in the SDNoC architecture where researchers may contribute to Many-Core SoCs designs.


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