This paper presents an efficient method for Regular Expression Matching (REM) by reusing Intellectual Property
(IP) cores in a new architecture of Network on Chip (NoC). The method is to design a reusable IP core which consists
of many engine cells for REM and to implement each engine cell on a Field Programmable Gate Array (FPGA) as a prototype.
To make Finite State Machine (FSM) simpler, a new approach for partitioning a regular expression into several
smaller parts is proposed. Each part of a regular expression was matched by an engine cell during matching, and each engine
cell communicates with others by routers on a NoC topology. The proposed NoC architecture is a general-purpose
design which is suitable for different rule libraries in deep packet inspection (DPI). It can deal with the problem that character
self-deplete made the correct regular expression matching missing. A way to use both logic cell and RAM available
on FPGA devices is described, and it can make it easier to change the rule library of regular expressions in the RAM. The
implementation of the NoC architecture by employing application-specific integrated circuits (ASIC) is finally discussed.
Design of a Regular Expression Matching System Based on Network on Chip
