Early Design Space Exploration Framework for Memristive Crossbar Arrays

2022 ◽  
Vol 18 (2) ◽  
pp. 1-26
Author(s):  
Md Adnan Zaman ◽  
Rajeev Joshi ◽  
Srinivas Katkoori

For memristive crossbar arrays, currently, no high-level design validation and early space exploration tools exist in the literature. Such tools are essential to quickly verify the design functionality as well as compare design alternatives in terms of power and performance. In this work, we propose a VHDL-based framework that enables us to quickly perform behavioral simulation as well as estimate dynamic energy consumption and speed of any large memristive crossbar array. We propose a high-level (VHDL) model of a memristor based on which crossbar architectures can be modeled. The individual memristor model is embedded with power and delay numbers obtained from a detailed memristor model. We demonstrate the framework for MAGIC-style memristive crossbars. We validate the framework against detailed Verilog-A based model on fifteen combinational benchmarks. For the single row model, we obtained 153x simulation speedup over HSPICE, average estimation errors of 6.64% and 0% for dynamic energy consumption and cycle-time, respectively. For the transpose model, we obtained average estimation errors of 5.51% and 10.90% for dynamic energy consumption and cycle-time, respectively. We also extend our framework to support another prominent logic style and validate through a case study. The proposed framework can be easily extended to other emerging technologies.

2021 ◽  
Author(s):  
Aakriti Tarun Sharma

The process of converting a behavioral specification of an application to its equivalent system architecture is referred to as High Level-Synthesis (HLS). A crucial stage in embedded systems design involves finding the trade off between resource utilization and performance. An exhaustive search would yield the required results, but would take a huge amount of time to arrive at the solution even for smaller designs. This would result in a high time complexity. We employ the use of Design Space Exploration (DSE) in order to reduce the complexity of the design space and to reach the desired results in less time. In reality, there are multiple constraints defined by the user that need to be satisfied simultaneously. Thus, the nature of the task at hand is referred to as Multi-Objective Optimization. In this thesis, the design process of DSP benchmarks was analyzed based on user defined constraints such as power and execution time. The analyzed outcome was compared with the existing approaches in DSE and an optimal design solution was derived in a shorter time period.


Author(s):  
Pablo Bellocq ◽  
Inaki Garmendia ◽  
Jordane Legrand ◽  
Vishal Sethi

Direct Drive Open Rotors (DDORs) have the potential to significantly reduce fuel consumption and emissions relative to conventional turbofans. However, this engine architecture presents many design and operational challenges both at engine and aircraft level. At preliminary design stages, a broad design space exploration is required to identify potential optimum design regions and to understand the main trade offs of this novel engine architecture. These assessments may also aid the development process when compromises need to be performed as a consequence of design, operational or regulatory constraints. Design space exploration assessments are done with 0-D or 1-D models for computational purposes. These simplified 0-D and 1-D models have to capture the impact of the independent variation of the main design and control variables of the engine. Historically, it appears that for preliminary design studies of DDORs, Counter Rotating Turbines (CRTs) have been modelled as conventional turbines and therefore it was not possible to assess the impact of the variation of the number of stages (Nb) of the CRT and rotational speed of the propellers. Additionally, no preliminary design methodology for CRTs was found in the public domain. Part I of this two-part publication proposes a 1-D preliminary design methodology for DDOR CRTs which allows an independent definition of both parts of the CRT. A method for calculating the off-design performance of a known CRT design is also described. In Part II, a 0-D design point efficiency calculation for CRTs is proposed and verified with the 1-D methods. The 1-D and 0-D CRT models were used in an engine control and design space exploration case study of a DDOR with a 4.26m diameter an 10% clipped propeller for a 160 PAX aircraft. For this application: • the design and performance of a 20 stage CRT rotating at 860 rpm (both drums) obtained with the 1-D methods is presented. • differently from geared open rotors, negligible cruise fuel savings can be achieved by an advanced propeller control. • for rotational speeds between 750 and 880 rpm (relatively low speeds for reduced noise), 22 and 20 stages CRTs are required. • engine weight can be kept constant for different design rotational speeds by using the minimum required Nb. • for any target engine weight, TOC and cruise SFC are reduced by reducing the rotational speeds and increasing Nb (also favourable for reducing CRP noise). However additional CRT stages increase engine drag, mechanical complexity and cost.


2021 ◽  
Author(s):  
Aakriti Tarun Sharma

The process of converting a behavioral specification of an application to its equivalent system architecture is referred to as High Level-Synthesis (HLS). A crucial stage in embedded systems design involves finding the trade off between resource utilization and performance. An exhaustive search would yield the required results, but would take a huge amount of time to arrive at the solution even for smaller designs. This would result in a high time complexity. We employ the use of Design Space Exploration (DSE) in order to reduce the complexity of the design space and to reach the desired results in less time. In reality, there are multiple constraints defined by the user that need to be satisfied simultaneously. Thus, the nature of the task at hand is referred to as Multi-Objective Optimization. In this thesis, the design process of DSP benchmarks was analyzed based on user defined constraints such as power and execution time. The analyzed outcome was compared with the existing approaches in DSE and an optimal design solution was derived in a shorter time period.


Author(s):  
Nicolas Albarello ◽  
Jean-Baptiste Welcomme

The design of systems architectures often involve a combinatorial design-space made of technological and architectural choices. A complete or large exploration of this design space requires the use of a method to generate and evaluate design alternatives. This paper proposes an innovative approach for the design-space exploration of systems architectures. The SAMOA (System Architecture Model-based OptimizAtion) tool associated to the method is also introduced. The method permits to create a large number of various system architectures combining a set of possible components to address given system functions. The method relies on models that are used to represent the problem and the solutions and to evaluate architecture performances. An algorithm first synthesizes design alternatives (a physical architecture associated to a functional allocation) based on the functional architecture of the system, the system interfaces, a library of available components and user-defined design rules. Chains of components are sequentially added to an initially empty architecture until all functions are fulfilled. The design rules permit to guarantee the viability and validity of the chains of components and, consequently, of the generated architectures. The design space exploration is then performed in a smart way through the use of an evolutionary algorithm, the evolution mechanisms of which are specific to system architecting. Evaluation modules permit to assess the performances of alternatives based on the structure of the architecture model and the data embedded in the component models. These performances are used to select the best generated architectures considering constraints and quality metrics. This selection is based on the Pareto-dominance-based NSGA-II algorithm or, alternatively, on an interactive preference-based algorithm. Iterating over this evolution-evaluation-selection process permits to increase the quality of solutions and, thus, to highlight the regions of interest of the design-space which can be used as a base for further manual investigations. By using this method, the system designers have a larger confidence in the optimality of the adopted architecture than using a classical derivative approach as many more solutions are evaluated. Also, the method permits to quickly evaluate the trade-offs between the different considered criteria. Finally, the method can also be used to evaluate the impact of a technology on the system performances not only by a substituting a technology by another but also by adapting the architecture of the system.


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