Critical-weight based locking scheme for DNN IP protection in edge computing

2021 ◽  
Author(s):  
Ziwei Song ◽  
Wei Jiang ◽  
Jinyu Zhan ◽  
Xiangyu Wen ◽  
Chen Bian
2020 ◽  
Vol 140 (9) ◽  
pp. 1030-1039
Author(s):  
W.A. Shanaka P. Abeysiriwardhana ◽  
Janaka L. Wijekoon ◽  
Hiroaki Nishi

Author(s):  
Ping ZHAO ◽  
Jiawei TAO ◽  
Abdul RAUF ◽  
Fengde JIA ◽  
Longting XU

Author(s):  
Adyson Magalhaes Maia ◽  
Yacine Ghamri-Doudane ◽  
Dario Vieira ◽  
Miguel Franklin de Castro

Author(s):  
Mai Zhihong ◽  
Ng Tsu Hau ◽  
Dawood M. Khalid ◽  
Tan Pik Kee ◽  
Jeffrey Lam

Abstract IP protection is of major importance for a semiconductor company and only limited information is made available for device debugging for the product outsourced to a foundry. In order to position ourselves better in the ever competitive semiconductor industry, with the consideration of IP protection, we have to provide the customers with the Si debugging capability and device/chip verification services in foundry. This paper explores the Si debugging methodology and technique in a foundry. Two case studies are presented and discussed. The first case illustrates the isolation of the failure location by InGaAs microscopy, upon which the failure was identified to be caused by a latch-up issue. In the second case, due to confidentiality considerations from the customer, full information could not be provided to the foundry for silicon debugging. The paper illustrates the ability to effectively debug a failure despite being constrained by limited information from the customer.


Author(s):  
Da-Yin Liao

Contemporary 300mm semiconductor manufacturing systems have highly automated and digitalized cyber-physical integration. They suffer from the profound problems of integrating large, centralized legacy systems with small islands of automation. With the recent advances in disruptive technologies, semiconductor manufacturing has faced dramatic pressures to reengineer its automation and computer integrated systems. This paper proposes a Distributed-Ledger, Edge-Computing Architecture (DLECA) for automation and computer integration in semiconductor manufacturing. Based on distributed ledger and edge computing technologies, DLECA establishes a decentralized software framework where manufacturing data are stored in distributed ledgers and processed locally by executing smart contracts at the edge nodes. We adopt an important topic of automation and computer integration for semiconductor research &development (R&D) operations as the study vehicle to illustrate the operational structure and functionality, applications, and feasibility of the proposed DLECA software framework.


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