Prediction of Static Characteristic Parameters of an Insulated Gate Bipolar Transistor Using Artificial Neural Network

Breakdown voltage (BV), on-state voltage (Von), static latch-up voltage (Vlu), static latch-up current density (Jlu), and threshold voltage (Vth), etc., are critical static characteristic parameters of an IGBT for researchers. Von and Vth can characterize the conduction capability of the device, while BV, Vlu, and Jlu can help designers analyze the safe operating area (SOA) of the device and its reliability. In this paper, we propose a multi-layer artificial neural network (ANN) framework to predict these characteristic parameters. The proposed scheme can accurately fit the relationship between structural parameters and static characteristic parameters. Given the structural parameters of the device, characteristic parameters can be generated accurately and efficiently. Compared with technology computer-aided design (TCAD) simulation, the average errors of our scheme for each characteristic parameter are within 8%, especially for BV and Vth, while the errors are controlled within 1%, and the evaluation speed is improved more than 107 times. In addition, since the prediction process is mathematically a matrix operation process, there is no convergence problem, which there is in a TCAD simulation.

Single event latch-up detection for nano-satellite external solar radiation mitigation system

This paper presents the single event latch-up (SEL) detection for nano-satellite external solar radiation mitigation system. In this study, the SEL detection analysis was conducted using circuit test and simulation. An electrical power subsystem (EPS) is a part of all CubeSat bus subsystems and it comprises solar arrays, rechargeable batteries, and a power control and distribution unit (PCDU). In order to extract the maximum power generated by the solar arrays, a peak power tracking topology is required. This may lead to the SEL with the presence of high voltage produced by solar. To overcome the SEL problems, the circuit test and simulation must be done so that the flow of SEL will be easily detected and mitigate. The method that been used are by using microcontroller, the SEL will be created in the certain time. The programable integrated circuit (PIC) are used to mitigate SEL effect. It indicates that, the SEL occur very fast in certain time. When the simulation is conducted by using SPENVIS, the result shows, only single event upset (SEU) was affected on UiTMSAT-1.

Robust and Latch-Up-Immune LVTSCR Device with an Embedded PMOSFET for ESD Protection in a 28-nm CMOS Process

Low-voltage-triggered silicon-controlled rectifier (LVTSCR) is expected to provide an electrostatic discharge (ESD) protection for a low-voltage integrated circuit. However, it is normally vulnerable to the latch-up effect due to its extremely low holding voltage. In this paper, a novel LVTSCR embedded with an extra p-type MOSFET called EP-LVTSCR has been proposed and verified in a 28-nm CMOS technology. The proposed device possesses a lower trigger voltage of ~ 6.2 V and a significantly higher holding voltage of ~ 5.5 V with only 23% degradation of the failure current under the transmission line pulse test. It is also shown that the EP-LVTSCR operates with a lower turn-on resistance of ~ 1.8 Ω as well as a reliable leakage current of ~ 1.8 nA measured at 3.63 V, making it suitable for ESD protections in 2.5 V/3.3 V CMOS processes. Moreover, the triggering mechanism and conduction characteristics of the proposed device were explored and demonstrated with TCAD simulation.