scholarly journals Analysis and Enhancement of Random Number Generator in FPGA Based on Oscillator Rings

2009 ◽  
Vol 2009 ◽  
pp. 1-8 ◽  
Author(s):  
Knut Wold ◽  
Chik How Tan

A true random number generator (TRNG) is an important component in cryptographic systems. Designing a fast and secure TRNG in an FPGA is a challenging task. In this paper, we analyze the TRNG designed by Sunar et al. (2007) based on XOR of the outputs of several oscillator rings. We propose an enhanced TRNG with better randomness characteristics that does not require postprocessing and passes the statistical tests. We have shown by experiment that the frequencies of the equal length oscillator rings in the TRNG are not identical. The difference is due to the placement of the inverters in the FPGA and the resulting routing between the inverters. We have implemented our proposed TRNG in an Altera Cyclone II FPGA. Our implementation has passed the NIST and DIEHARD statistical tests with a throughput of 100 Mbps and with a usage of less than 100 logic elements in the FPGA. The restart experiments have shown that the output from our TRNG behaves truly random and not pseudorandom.

2020 ◽  
Author(s):  
Scott Stoller

Random numbers are an important, but often overlooked part of the modern computing environment. They are used everywhere around us for a variety of purposes, from simple decision making in video games such as a coin toss, to securing financial transactions and encrypting confidential communications. They are even useful for gambling and the lottery. Random numbers are generated in many ways. Pseudo random number generators (PRNGs) generate numbers based on a formula. True random number generators (TRNGs) capture entropy from the environment to generate randomness. As our society and our devices become more connected in the digital world, it is important to develop new ways to generate truly random numbers in order to secure communications and connected devices. In this work a novel memristor-based True Random Number Generator is designed and a physical implementation is fabricated and tested using a W-based self-directed channel (SDC) memristor. The circuit was initially designed and prototyped on a breadboard. A custom Printed Circuit Board (PCB) was fabricated for the final circuit design and testing of the novel memristor-based TRNG. The National Institute of Standards and Technology (NIST) Statistical Test Suite (STS) was used to check the output of the TRNG for randomness. The TRNG was demonstrated to pass 13 statistical tests out of the 15 in the STS.


Author(s):  
Noor Alia Nor Hashim ◽  
Julius Teo Han Loong ◽  
Azrul Ghazali ◽  
Fazrena Azlee Hamid

<span>Cryptographic applications require numbers that are random and pseudorandom. Keys must be produced in a random manner in order to be used in common cryptosystems. Random or pseudorandom inputs at different terminals are also required in a lot of cryptographic protocols. For example, producing digital signatures using supporting quantities or in verification procedures that requires generating challenges. Random number generation is an important part of cryptography because there are flaws in random number generation that can be taken advantage by attackers that compromised encryption systems that are algorithmically secure. True random number generators (TRNGs) are the best in producing random numbers. This paper presents a True Random Number Generator that uses memristor based ring oscillators in the design. The designs are implemented in 0.18 µm complementary metal oxide semiconductor (CMOS) technology using LT SPICE IV. Different window functions for the memristor model was applied to the TRNG and compared. Statistical tests results of the output random numbers produced showed that the proposed TRNG design can produce random output regardless of the window function.</span>


2020 ◽  
Vol 14 (7) ◽  
pp. 1001-1011
Author(s):  
Dhirendra Kumar ◽  
Rahul Anand ◽  
Sajai Vir Singh ◽  
Prasanna Kumar Misra ◽  
Ashok Srivastava ◽  
...  

2021 ◽  
pp. 2100062
Author(s):  
Kyung Seok Woo ◽  
Jaehyun Kim ◽  
Janguk Han ◽  
Jin Myung Choi ◽  
Woohyun Kim ◽  
...  

2021 ◽  
Vol 11 (8) ◽  
pp. 3330
Author(s):  
Pietro Nannipieri ◽  
Stefano Di Matteo ◽  
Luca Baldanzi ◽  
Luca Crocetti ◽  
Jacopo Belli ◽  
...  

Random numbers are widely employed in cryptography and security applications. If the generation process is weak, the whole chain of security can be compromised: these weaknesses could be exploited by an attacker to retrieve the information, breaking even the most robust implementation of a cipher. Due to their intrinsic close relationship with analogue parameters of the circuit, True Random Number Generators are usually tailored on specific silicon technology and are not easily scalable on programmable hardware, without affecting their entropy. On the other hand, programmable hardware and programmable System on Chip are gaining large adoption rate, also in security critical application, where high quality random number generation is mandatory. The work presented herein describes the design and the validation of a digital True Random Number Generator for cryptographically secure applications on Field Programmable Gate Array. After a preliminary study of literature and standards specifying requirements for random number generation, the design flow is illustrated, from specifications definition to the synthesis phase. Several solutions have been studied to assess their performances on a Field Programmable Gate Array device, with the aim to select the highest performance architecture. The proposed designs have been tested and validated, employing official test suites released by NIST standardization body, assessing the independence from the place and route and the randomness degree of the generated output. An architecture derived from the Fibonacci-Galois Ring Oscillator has been selected and synthesized on Intel Stratix IV, supporting throughput up to 400 Mbps. The achieved entropy in the best configuration is greater than 0.995.


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