scholarly journals Memristor based ring oscillators true random number generator with different window functions for applications in cryptography

Author(s):  
Noor Alia Nor Hashim ◽  
Julius Teo Han Loong ◽  
Azrul Ghazali ◽  
Fazrena Azlee Hamid

<span>Cryptographic applications require numbers that are random and pseudorandom. Keys must be produced in a random manner in order to be used in common cryptosystems. Random or pseudorandom inputs at different terminals are also required in a lot of cryptographic protocols. For example, producing digital signatures using supporting quantities or in verification procedures that requires generating challenges. Random number generation is an important part of cryptography because there are flaws in random number generation that can be taken advantage by attackers that compromised encryption systems that are algorithmically secure. True random number generators (TRNGs) are the best in producing random numbers. This paper presents a True Random Number Generator that uses memristor based ring oscillators in the design. The designs are implemented in 0.18 µm complementary metal oxide semiconductor (CMOS) technology using LT SPICE IV. Different window functions for the memristor model was applied to the TRNG and compared. Statistical tests results of the output random numbers produced showed that the proposed TRNG design can produce random output regardless of the window function.</span>

2021 ◽  
Vol 11 (8) ◽  
pp. 3330
Author(s):  
Pietro Nannipieri ◽  
Stefano Di Matteo ◽  
Luca Baldanzi ◽  
Luca Crocetti ◽  
Jacopo Belli ◽  
...  

Random numbers are widely employed in cryptography and security applications. If the generation process is weak, the whole chain of security can be compromised: these weaknesses could be exploited by an attacker to retrieve the information, breaking even the most robust implementation of a cipher. Due to their intrinsic close relationship with analogue parameters of the circuit, True Random Number Generators are usually tailored on specific silicon technology and are not easily scalable on programmable hardware, without affecting their entropy. On the other hand, programmable hardware and programmable System on Chip are gaining large adoption rate, also in security critical application, where high quality random number generation is mandatory. The work presented herein describes the design and the validation of a digital True Random Number Generator for cryptographically secure applications on Field Programmable Gate Array. After a preliminary study of literature and standards specifying requirements for random number generation, the design flow is illustrated, from specifications definition to the synthesis phase. Several solutions have been studied to assess their performances on a Field Programmable Gate Array device, with the aim to select the highest performance architecture. The proposed designs have been tested and validated, employing official test suites released by NIST standardization body, assessing the independence from the place and route and the randomness degree of the generated output. An architecture derived from the Fibonacci-Galois Ring Oscillator has been selected and synthesized on Intel Stratix IV, supporting throughput up to 400 Mbps. The achieved entropy in the best configuration is greater than 0.995.


2015 ◽  
Vol 61 (2) ◽  
pp. 199-204 ◽  
Author(s):  
Szymon Łoza ◽  
Łukasz Matuszewski ◽  
Mieczysław Jessa

Abstract Today, cryptographic security depends primarily on having strong keys and keeping them secret. The keys should be produced by a reliable and robust to external manipulations generators of random numbers. To hamper different attacks, the generators should be implemented in the same chip as a cryptographic system using random numbers. It forces a designer to create a random number generator purely digitally. Unfortunately, the obtained sequences are biased and do not pass many statistical tests. Therefore an output of the random number generator has to be subjected to a transformation called post-processing. In this paper the hash function SHA-256 as post-processing of bits produced by a combined random bit generator using jitter observed in ring oscillators (ROs) is proposed. All components – the random number generator and the SHA-256, are implemented in a single Field Programmable Gate Array (FPGA). We expect that the proposed solution, implemented in the same FPGA together with a cryptographic system, is more attack-resistant owing to many sources of randomness with significantly different nominal frequencies.


Author(s):  
Kentaro Tamura ◽  
Yutaka Shikano

Abstract A cloud quantum computer is similar to a random number generator in that its physical mechanism is inaccessible to its users. In this respect, a cloud quantum computer is a black box. In both devices, its users decide the device condition from the output. A framework to achieve this exists in the field of random number generation in the form of statistical tests for random number generators. In the present study, we generated random numbers on a 20-qubit cloud quantum computer and evaluated the condition and stability of its qubits using statistical tests for random number generators. As a result, we observed that some qubits were more biased than others. Statistical tests for random number generators may provide a simple indicator of qubit condition and stability, enabling users to decide for themselves which qubits inside a cloud quantum computer to use.


2020 ◽  
Author(s):  
Scott Stoller

Random numbers are an important, but often overlooked part of the modern computing environment. They are used everywhere around us for a variety of purposes, from simple decision making in video games such as a coin toss, to securing financial transactions and encrypting confidential communications. They are even useful for gambling and the lottery. Random numbers are generated in many ways. Pseudo random number generators (PRNGs) generate numbers based on a formula. True random number generators (TRNGs) capture entropy from the environment to generate randomness. As our society and our devices become more connected in the digital world, it is important to develop new ways to generate truly random numbers in order to secure communications and connected devices. In this work a novel memristor-based True Random Number Generator is designed and a physical implementation is fabricated and tested using a W-based self-directed channel (SDC) memristor. The circuit was initially designed and prototyped on a breadboard. A custom Printed Circuit Board (PCB) was fabricated for the final circuit design and testing of the novel memristor-based TRNG. The National Institute of Standards and Technology (NIST) Statistical Test Suite (STS) was used to check the output of the TRNG for randomness. The TRNG was demonstrated to pass 13 statistical tests out of the 15 in the STS.


2019 ◽  
Vol 8 (2) ◽  
pp. 1-5
Author(s):  
Rajashree Chaurasia

Most programming languages have in-built functions for the sole purpose of generating pseudo-random numbers. This manuscript is aimed at analyzing the appropriateness of some of these in-built functions for some basic goodness-of-fit statistical tests for random number generators. The document is divided into four sections. The first section gives a broad introduction about randomness and the methods of generation of pseudo-random numbers. Section two discusses the statistical tests that were employed for testing the built-in library functions for random number generation. This section is followed by an analysis of the data collected for the various statistics in the third section, and lastly, the fourth section presents the results of the data analysis.


2020 ◽  
Author(s):  
Gwangmin Kim ◽  
Jae Hyun In ◽  
Hakseung Rhee ◽  
Woojoon Park ◽  
Hanchan Song ◽  
...  

Abstract The intrinsic stochasticity of the memristor can be used to generate true random numbers, essential for non-decryptable hardware-based security devices. Here we propose a novel and advanced method to generate true random numbers utilizing the stochastic oscillation behavior of a NbOx mott memristor, exhibiting self-clocking, fast and variation tolerant characteristics. The random number generation rate of the device can be at least 40 kbs-1, which is the fastest record compared with previous volatile memristor-based TRNG devices. Also, its dimensionless operating principle provides high tolerance against both ambient temperature variation and device-to-device variation, enabling robust security hardware applicable in harsh environments.


2017 ◽  
Vol 28 (06) ◽  
pp. 1750078 ◽  
Author(s):  
Kamalika Bhattacharjee ◽  
Dipanjyoti Paul ◽  
Sukanta Das

This paper investigates the potentiality of pseudo-random number generation of a 3-neighborhood 3-state cellular automaton (CA) under periodic boundary condition. Theoretical and empirical tests are performed on the numbers, generated by the CA, to observe the quality of it as pseudo-random number generator (PRNG). We analyze the strength and weakness of the proposed PRNG and conclude that the selected CA is a good random number generator.


2014 ◽  
Vol 573 ◽  
pp. 181-186 ◽  
Author(s):  
G.P. Ramesh ◽  
A. Rajan

—Field-programmable gate array (FPGA) optimized random number generators (RNGs) are more resource-efficient than software-optimized RNGs because they can take advantage of bitwise operations and FPGA-specific features. A random number generator (RNG) is a computational or physical device designed to generate a sequence of numbers or symbols that lack any pattern, i.e. appear random. The many applications of randomness have led to the development of several different methods for generating random data. Several computational methods for random number generation exist, but often fall short of the goal of true randomness though they may meet, with varying success, some of the statistical tests for randomness intended to measure how unpredictable their results are (that is, to what degree their patterns are discernible).LUT-SR Family of Uniform Random Number Generators are able to handle randomness only based on seeds that is loaded in the look up table. To make random generation efficient, we propose new approach based on SRAM storage device.Keywords: RNG, LFSR, SRAM


Sensors ◽  
2020 ◽  
Vol 20 (7) ◽  
pp. 1869 ◽  
Author(s):  
Luca Baldanzi ◽  
Luca Crocetti ◽  
Francesco Falaschi ◽  
Matteo Bertolucci ◽  
Jacopo Belli ◽  
...  

In the context of growing the adoption of advanced sensors and systems for active vehicle safety and driver assistance, an increasingly important issue is the security of the information exchanged between the different sub-systems of the vehicle. Random number generation is crucial in modern encryption and security applications as it is a critical task from the point of view of the robustness of the security chain. Random numbers are in fact used to generate the encryption keys to be used for ciphers. Consequently, any weakness in the key generation process can potentially leak information that can be used to breach even the strongest cipher. This paper presents the architecture of a high performance Random Number Generator (RNG) IP-core, in particular a Cryptographically Secure Pseudo-Random Number Generator (CSPRNG) IP-core, a digital hardware accelerator for random numbers generation which can be employed for cryptographically secure applications. The specifications used to develop the proposed project were derived from dedicated literature and standards. Subsequently, specific architecture optimizations were studied to achieve better timing performance and very high throughput values. The IP-core has been validated thanks to the official NIST Statistical Test Suite, in order to evaluate the degree of randomness of the numbers generated in output. Finally the CSPRNG IP-core has been characterized on relevant Field Programmable Gate Array (FPGA) and ASIC standard-cell technologies.


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