An FPGA Based Open Source Network-on-Chip Architecture

2007 ◽  
Author(s):  
Andreas Ehliar ◽  
Dake Liu
Keyword(s):  
Open Source ◽  
Network On Chip ◽  
On Chip

scholarly journals Design Environment for Verilog Module Analysis using Open Source Tools

2019 ◽  
Vol 9 (2S) ◽  
pp. 109-112
Keyword(s):  
Energy Efficiency ◽  
Life Cycle ◽  
Open Source ◽  
Product Life Cycle ◽  
Semiconductor Industry ◽  
Network On Chip ◽  
Design Environment ◽  
Time To Market ◽  
Distributed Routing ◽  
On Chip

Network-on-Chip provides possible solutions for the limitations and challenges by the present day architectures for the interconnections. The characteristics of NoCs include energy efficiency, reliability, scalability, reusability and distributed routing decisions. The existence of today’s semiconductor industry depends on shorter time-to-market, challenge of meeting increasing transistor density, reduced product life cycle, and operating frequencies getting higher. This paper discusses about a design environment for the analysis of Verilog NoC module. Tools such as Icarus Verilog, GTK Wave, Yosys etc. which are used for compilation, simulation and synthesis of the NoC are also discussed in this paper.

scholarly journals A Middleware Approach to Achieving Fault Tolerance of Kahn Process Networks on Networks on Chips

2011 ◽  
Vol 2011 ◽  
pp. 1-15 ◽  
Author(s):  
Onur Derin ◽  
Erkan Diken ◽  
Leandro Fiorin
Keyword(s):  
Fault Tolerance ◽  
Open Source ◽  
Execution Time ◽  
Initial Step ◽  
Network On Chip ◽  
Distributed Model ◽  
Total Execution Time ◽  
Process Networks ◽  
Kahn Process ◽  
On Chip

Kahn process networks (KPNs) is a distributed model of computation used for describing systems where streams of data are transformed by processes executing in sequence or parallel. Autonomous processes communicate through unbounded FIFO channels in absence of a global scheduler. In this work, we propose a task-aware middleware concept that allows adaptivity in KPN implemented over a Network on Chip (NoC). We also list our ideas on the development of a simulation platform as an initial step towards creating fault tolerance strategies for KPNs applications running on NoCs. In doing that, we extend our SACRE (Self-Adaptive Component Run Time Environment) framework by integrating it with an open source NoC simulator, Noxim. We evaluate the overhead that the middleware brings to the the total execution time and to the total amount of data transferred in the NoC. With this work, we also provide a methodology that can help in identifying the requirements and implementing fault tolerance and adaptivity support on real platforms.

Pre-allocated Path Based Low Latency Router Architecture for Network-on-chip

2014 ◽  
Vol 35 (2) ◽  
pp. 341-346
Author(s):  
Xiao-fu Zheng ◽  
Hua-xi Gu ◽  
Yin-tang Yang ◽  
Zhong-fan Huang
Keyword(s):  
Network On Chip ◽  
Low Latency ◽  
Router Architecture ◽  
On Chip

scholarly journals On the Cooperative Relaying Strategies for Multi-Core Wireless Network-on-Chip

IEEE Access ◽  
2021 ◽  
pp. 1-1
Author(s):  
Quoc-Tuan Vien ◽  
Michael Opoku Agyeman ◽  
Mallik Tatipamula ◽  
Huan X. Nguyen
Keyword(s):  
Wireless Network ◽  
Network On Chip ◽  
Cooperative Relaying ◽  
On Chip ◽  
Relaying Strategies
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