scholarly journals Comparative Analysis of Different PWM Techniques to Reduce the Common Mode Voltage in Three-Level Neutral-Point-Clamped Inverters for Variable Speed Induction Drives

2013 ◽  
Vol 3 (1) ◽  
Author(s):  
Bharati Raja ◽  
S. Raghu
Keyword(s):  
Comparative Analysis ◽  
Neutral Point ◽  
Variable Speed ◽  
Common Mode ◽  
Common Mode Voltage ◽  
The Common

scholarly journals Modeling and Modulation of NNPC Four-Level Inverter for Solar Photovoltaic Power Plant

2017 ◽  
Vol 2017 ◽  
pp. 1-8 ◽  
Author(s):  
Xiaoqiang Guo ◽  
Xuehui Wang ◽  
Ran He ◽  
Mehdi Narimani
Keyword(s):  
Power Plant ◽  
Neutral Point ◽  
Multilevel Inverter ◽  
Solar Photovoltaic ◽  
Common Mode ◽  
Practical Applications ◽  
Common Mode Voltage ◽  
Photovoltaic Power ◽  
The Common ◽  
Conventional Solution

Photovoltaic (PV) power plant is an attractive way of utilizing the solar energy. For high-power PV power plant, the multilevel inverter is of potential interest. In contrast to the neutral-point clamped (NPC) or flying capacitor (FC) multilevel inverter, the nested neutral point clamped (NNPC) four-level inverter has better features for solar photovoltaic power plant. In practical applications, the common mode voltage reduction of the NNPC four-level is one of the important issues. In order to solve the problem, a new modulation strategy is proposed to minimize the common mode voltage. Compared with the conventional solution, our proposal can reduce the common mode voltage to 1/18 of the DC bus voltage. Moreover, it has the capability to balance the capacitor voltages. Finally, we carried out time-domain simulations to test the performance of the NNPC four-level inverter.

scholarly journals A Method for the Simultaneous Suppression of DC Capacitor Fluctuations and Common-Mode Voltage in a Five-Level NPC/H Bridge Inverter

Energies ◽  
2019 ◽  
Vol 12 (5) ◽  
pp. 779 ◽  
Author(s):  
Ming Wu ◽  
Zhenhao Song ◽  
Zhipeng Lv ◽  
Kai Zhou ◽  
Qi Cui
Keyword(s):  
Pulse Width Modulation ◽  
Neutral Point ◽  
Common Mode ◽  
Mapping Algorithm ◽  
Common Mode Voltage ◽  
Point Potential ◽  
Voltage Vector ◽  
Three Phase ◽  
Simulation And Experiment ◽  
The Common

To suppress the direct current (DC) capacitor voltage fluctuations and the common-mode voltage (CMV) in a three-phase, five-level, neutral-point-clamped (NPC)/H-bridge inverter, this paper analyzes the influence of all voltage vectors on the neutral point potential of each phase under different pulse mappings in detail with an explanation of the CMV distribution. Then, based on the traditional space vector pulse width modulation (SVPWM) algorithm, a dual-pulse-mapping algorithm is proposed to suppress the DC capacitor fluctuations and the CMV simultaneously. In the algorithm, the reference voltage synthesis selects the voltage vector that has the smallest CMV value as the priority. In addition, the two kinds of pulse mappings that have opposite effects on the neutral point potential are switched to output. At the same time, regulating factors are introduced to adjust the working time of each voltage vector under the two pulse mappings; then, the capacitor voltages can be balanced. Both the simulation and experiment demonstrate the algorithm’s effectiveness.

Investigation of the Common Mode Voltage for a Neutral-Point-Clamped Multilevel Inverter Drive and its Innovative Elimination through SVPWM Switching-State Redundancy

2016 ◽  
Vol 7 (3) ◽  
pp. 892
Author(s):  
C. Bharatiraja ◽  
J.L. Munda ◽  
N. Sriramsai ◽  
T Sai Navaneesh
Keyword(s):  
Pulse Width Modulation ◽  
Selection Procedure ◽  
Neutral Point ◽  
Multilevel Inverter ◽  
Common Mode ◽  
Common Mode Voltage ◽  
Three Phase ◽  
Theoretical Investigations ◽  
Field Programmable ◽  
The Common

The purpose of this paper is to provide a comprehensive Investigations and its control on the common mode Voltage (CMV) of the three-phase three-level neutral-point diode-clamped (NPC) multilevel inverter (MLI). A widespread space-vector pulse width modulation (SVPWM) technique to mitigate the perpetual problem of the NPC-MLI, the CMV, proposed. The proposed scheme is an effectual blend of nearest three vector (NTV) and selected three vector (STV) techniques. This scheme is capable to reduce the CMV without compromise the inverter output voltage and Total harmonics distraction (THD). CMV reduction achieved less than +Vdc/6 using the proposed vector selection procedure. The theoretical Investigations, the MATLAB software based computer simulation and Field Programmable Gate Array (FPGA) supported hardware corroboration have shown the superiority of the proposed technique over the conventional SVPWM schemes.

scholarly journals Common-Mode Voltage Harmonic Reduction in Variable Speed Drives Applying a Variable-Angle Carrier Phase-Displacement PWM Method

Energies ◽  
2021 ◽  
Vol 14 (10) ◽  
pp. 2929
Author(s):  
Abraham Marquez Alcaide ◽  
Vito Giuseppe Monopoli ◽  
Xuchen Wang ◽  
Jose I. Leon ◽  
Giampaolo Buticchi ◽  
...  
Keyword(s):  
Carrier Phase ◽  
Harmonic Distortion ◽  
Harmonic Spectrum ◽  
Hydraulic Systems ◽  
Variable Speed ◽  
Common Mode ◽  
Variable Speed Drives ◽  
Phase Displacement ◽  
Common Mode Voltage ◽  
External Component

Electric variable speed drives (VSD) have been replacing mechanic and hydraulic systems in many sectors of industry and transportation because of their better performance and reduced cost. However, the electric systems still face the issue of being considered less reliable than the mechanical ones. For this reason, researchers have been actively investigating effective ways to increase the reliability of such systems. This paper is focused on the analysis of the common-mode voltage (CMV) generated by the operation of the VSDs which directly affects to the lifetime and reliability of the complete system. The method is based on the mathematical description of the harmonic spectrum of the CMV depending on the PWM method implementation. A generalized PWM method where the carriers present a variable phase-displacement is developed. As a result of the presented analysis, the CMV reduction is achieved by applying the PWM method with optimal carrier phase-displacement angles without any external component and/or passive filtering technique. The optimal values of the carrier phase-displacement angles are obtained considering the minimization of the CMV total harmonic distortion. The resulting method is easily implementable on mostly off-the-shelf mid-range micro-controller control platforms. The strategy has been evaluated in a scaled-down experimental setup proving its good performance.

scholarly journals A New Approach to the PWM Modulation for the Multiphase Matrix Converters Supplying Loads with Open-End Winding

Energies ◽  
2021 ◽  
Vol 14 (2) ◽  
pp. 466
Author(s):  
Pawel Szczepankowski ◽  
Natalia Strzelecka ◽  
Enrique Romero-Cadaval
Keyword(s):  
Pulse Width Modulation ◽  
Harmonic Distortion ◽  
Simulation Software ◽  
Common Mode ◽  
New Approach ◽  
Matrix Converters ◽  
Load Voltage ◽  
Common Mode Voltage ◽  
The Common ◽  
Open End Winding

This article presents three variants of the Pulse Width Modulation (PWM) for the Double Square Multiphase type Conventional Matrix Converters (DSM-CMC) supplying loads with the open-end winding. The first variant of PWM offers the ability to obtain zero value of the common-mode voltage at the load’s terminals and applies only six switches within the modulation period. The second proposal archives for less Total Harmonic Distortion (THD) of the generated load voltage. The third variant of modulation concerns maximizing the voltage transfer ratio, minimizing the number of switching, and the common-mode voltage cancellation. The discussed modulations are based on the concept of sinusoidal voltage quadrature signals, which can be an effective alternative to the classic space-vector approach. In the proposed approach, the geometrical arrangement of basic vectors needed to synthesize output voltages is built from the less number of vectors, which is equal to the number of the matrix converter’s terminals. The PWM duty cycle computation is performed using only a second-order determinant of the voltages coordinate matrix without using trigonometric functions. A new approach to the PWM duty cycles computing and the load voltage synthesis by 5 × 5 and 12 × 12 topologies has been verified using the PSIM simulation software.

scholarly journals Opposite Triangle Carrier with SVPWM for Common-Mode Voltage Reduction in Dual Three Phase Motor Drives

Energies ◽  
2021 ◽  
Vol 14 (2) ◽  
pp. 282
Author(s):  
Seon-Ik Hwang ◽  
Jang-Mok Kim
Keyword(s):  
Electromagnetic Interference ◽  
Pulse Width Modulation ◽  
Motor Drives ◽  
Common Mode ◽  
Pwm Inverter ◽  
Common Mode Voltage ◽  
Voltage Vector ◽  
Three Phase ◽  
The Common ◽  
Zero Voltage

The common-mode voltage (CMV) generated by the switching operation of the pulse width modulation (PWM) inverter leads to bearing failure and electromagnetic interference (EMI) noises. To reduce the CMV, it is necessary to reduce the magnitude of dv/dt and change the frequency of the CMV. In this paper, the range of the CMV is reduced by using opposite triangle carrier for ABC and XYZ winding group, and the change in frequency in the CMV is reduced by equalizing the dwell time of the zero voltage vector on ABC and XYZ winding group of dual three phase motor.

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