scholarly journals Opposite Triangle Carrier with SVPWM for Common-Mode Voltage Reduction in Dual Three Phase Motor Drives

Energies ◽  
2021 ◽  
Vol 14 (2) ◽  
pp. 282
Author(s):  
Seon-Ik Hwang ◽  
Jang-Mok Kim
Keyword(s):  
Electromagnetic Interference ◽  
Pulse Width Modulation ◽  
Motor Drives ◽  
Common Mode ◽  
Pwm Inverter ◽  
Common Mode Voltage ◽  
Voltage Vector ◽  
Three Phase ◽  
The Common ◽  
Zero Voltage

The common-mode voltage (CMV) generated by the switching operation of the pulse width modulation (PWM) inverter leads to bearing failure and electromagnetic interference (EMI) noises. To reduce the CMV, it is necessary to reduce the magnitude of dv/dt and change the frequency of the CMV. In this paper, the range of the CMV is reduced by using opposite triangle carrier for ABC and XYZ winding group, and the change in frequency in the CMV is reduced by equalizing the dwell time of the zero voltage vector on ABC and XYZ winding group of dual three phase motor.

scholarly journals A Method for the Simultaneous Suppression of DC Capacitor Fluctuations and Common-Mode Voltage in a Five-Level NPC/H Bridge Inverter

Energies ◽  
2019 ◽  
Vol 12 (5) ◽  
pp. 779 ◽  
Author(s):  
Ming Wu ◽  
Zhenhao Song ◽  
Zhipeng Lv ◽  
Kai Zhou ◽  
Qi Cui
Keyword(s):  
Pulse Width Modulation ◽  
Neutral Point ◽  
Common Mode ◽  
Mapping Algorithm ◽  
Common Mode Voltage ◽  
Point Potential ◽  
Voltage Vector ◽  
Three Phase ◽  
Simulation And Experiment ◽  
The Common

To suppress the direct current (DC) capacitor voltage fluctuations and the common-mode voltage (CMV) in a three-phase, five-level, neutral-point-clamped (NPC)/H-bridge inverter, this paper analyzes the influence of all voltage vectors on the neutral point potential of each phase under different pulse mappings in detail with an explanation of the CMV distribution. Then, based on the traditional space vector pulse width modulation (SVPWM) algorithm, a dual-pulse-mapping algorithm is proposed to suppress the DC capacitor fluctuations and the CMV simultaneously. In the algorithm, the reference voltage synthesis selects the voltage vector that has the smallest CMV value as the priority. In addition, the two kinds of pulse mappings that have opposite effects on the neutral point potential are switched to output. At the same time, regulating factors are introduced to adjust the working time of each voltage vector under the two pulse mappings; then, the capacitor voltages can be balanced. Both the simulation and experiment demonstrate the algorithm’s effectiveness.

scholarly journals Optimized Modulation Method for Common-Mode Voltage Reduction in H7 Inverter

Energies ◽  
2021 ◽  
Vol 14 (19) ◽  
pp. 6409
Author(s):  
Belete Belayneh Negesse ◽  
Chang-Hwan Park ◽  
Seung-Hwan Lee ◽  
Seon-Woong Hwang ◽  
Jang-Mok Kim
Keyword(s):  
Dwell Time ◽  
Pulse Width Modulation ◽  
Modulation Method ◽  
Limited Area ◽  
Common Mode ◽  
Common Mode Voltage ◽  
Offset Voltage ◽  
Voltage Vector ◽  
Three Phase ◽  
Zero Voltage

The three-phase H7 inverter topology installs an additional power semiconductor switch to the positive or negative node of the DC-link for reducing the common-mode voltage (CMV) by disconnecting the inverter from the DC source during the zero-voltage vectors. The conventional CMV reduction method for the three-phase H7 inverter uses modified discontinuous pulse width modulation (MDPWM) and generates a switching signal for the additional switch using logical operations. However, the conventional method is unable to eliminate the CMV for the entire dwell time of the zero-voltage vectors. It only has the effect of reducing the CMV in a limited area of the space vector where the V7 zero voltage vector is applied. Therefore, this paper proposes an optimized modulation method that can reduce the CMV during the entire dwell time of zero-voltage vectors. The proposed method moves the switching patterns by adding an offset voltage to guarantee that only one kind of zero-voltage vector, V7, is applied in the system. It then turns off the seventh switch only during the zero-voltage vector to disconnect the inverter from the DC source. As a result, the CMV and the leakage current are attenuated for the entire dwell time of the zero-voltage vector. Simulation and experimental results confirm the validity of the proposed method.

scholarly journals Remote-State PWM with Minimum RMS Torque Ripple and Reduced Common-Mode Voltage for Three-Phase VSI-Fed BLAC Motor Drives

Electronics ◽  
2020 ◽  
Vol 9 (4) ◽  
pp. 586 ◽  
Author(s):  
Jaehyuk Baik ◽  
Sangwon Yun ◽  
Dongsik Kim ◽  
Chunki Kwon ◽  
Jiyoon Yoo
Keyword(s):  
Pulse Width Modulation ◽  
Torque Ripple ◽  
Motor Drives ◽  
Voltage Source ◽  
Common Mode ◽  
Voltage Source Inverters ◽  
Common Mode Voltage ◽  
Voltage Vector ◽  
Three Phase ◽  
Current Ripple

A minimum root mean square (RMS) torque ripple-remote-state pulse-width modulation (MTR-RSPWM) technique is proposed for minimizing the RMS torque ripple under reduced common-mode voltage (CMV) condition of three-phase voltage source inverters (VSI)-fed brushless alternating current (BLAC) motor drives. The q-axis current ripple due to an error voltage vector generated between the reference voltage vector and applied voltage vector is analyzed for all pulse patterns with reduced CMV of the RSPWM. From the analysis result, in the MTR-RSPWM, a sector is divided into five zones, and within each zone, pulse patterns with the lowest RMS torque ripple and reduced CMV are employed. To verify the validity of the MTR-RSPWM, theorical analysis, simulation, and experiments are performed, where the MTR-RSPWM is thoroughly compared with RSPWM3 that generates the minimum RMS current ripple. From the analytical, simulation, and experimental results, it is shown that the MTR-RSPWM significantly reduces the RMS torque ripple under a reduced CMV condition at the expense of an increase in the RMS current ripple, compared to the RSPWM3.

scholarly journals Space-vector modulation for three-phase indirect matrix converters to reduce common-mode voltage

2021 ◽  
Vol 4 (2) ◽  
pp. first
Author(s):  
Hoan Quoc Tran ◽  
Tien Manh Vu ◽  
Tuyen Dinh Nguyen
Keyword(s):  
Matrix Converter ◽  
Space Vector Modulation ◽  
Space Vector ◽  
Common Mode ◽  
Common Mode Voltage ◽  
Output Performance ◽  
Three Phase ◽  
The Common ◽  
Vector Modulation ◽  
Zero Voltage

This paper presents a space vector modulation strategy for a three-phase indirect matrix converter to reduce the common-mode voltage and maintain the output performance. To reduce the peak value of the common-mode voltage to 57.7% of the input phase voltage, three active voltage vectors are used to generate the desired output voltage with arbitrary amplitude and frequency, instead of using both active and zero voltage vectors as in the traditional space vector modulation strategy. Although the common-mode voltage is reduced, the output waveform quality of the three-phase indirect matrix converter deteriorates due to the absence of the zero voltage vectors. To overcome this problem, the proposed space vector modulation strategy is redesigned to control the rectifier stage of the indirect matrix converter by utilizing three active current vectors instead of two as usual. Consequently, the constant average dc-link voltage is achieved, which can improve the output performance in terms of the output voltage and current harmonic distortion. The simulation is implemented by PSIM software and experimental results are provided to verify the effectiveness of the proposed space vector modulation strategy.

scholarly journals Ground Leakage Current Caused by Common-Mode Voltage of PWM inverter

2020 ◽  
Vol 1 (1) ◽  
pp. 15-25
Author(s):  
Jerzy Ryszard Szymański ◽  
Marta Żurek-Mortka
Keyword(s):  
Pulse Width Modulation ◽  
Differential Mode ◽  
Common Mode ◽  
Current Form ◽  
Pwm Inverter ◽  
Common Mode Voltage ◽  
Three Phase ◽  
Voltage Phase ◽  
Shock Protection ◽  
Parasitic Currents

In railway tractive vehicles, three-phase PWM (Pulse Width Modulation) inverters generate parasitic Differential-Mode Voltages (DMV) and Common-Mode Voltages (CMV). Parasitic voltages are a side effect of using the width modulation to shape the phase-to-phase inverter’s voltage. In this article, the authors present a mathematical description of the DM and CM voltages and carry out their spectral analysis. Based on the spectral harmonics analysis, the authors present a method for filtration of harmonics of DM and CM voltages aimed at limiting the capacitance parasitic currents: due to DM voltage – phase-to-phase parasitic current and CM voltage – ground parasitic currents. As the final result of the tests, almost complete elimination of leakage parasitic current form PE shock protection system was achieved.

Investigation of the Common Mode Voltage for a Neutral-Point-Clamped Multilevel Inverter Drive and its Innovative Elimination through SVPWM Switching-State Redundancy

2016 ◽  
Vol 7 (3) ◽  
pp. 892
Author(s):  
C. Bharatiraja ◽  
J.L. Munda ◽  
N. Sriramsai ◽  
T Sai Navaneesh
Keyword(s):  
Pulse Width Modulation ◽  
Selection Procedure ◽  
Neutral Point ◽  
Multilevel Inverter ◽  
Common Mode ◽  
Common Mode Voltage ◽  
Three Phase ◽  
Theoretical Investigations ◽  
Field Programmable ◽  
The Common

The purpose of this paper is to provide a comprehensive Investigations and its control on the common mode Voltage (CMV) of the three-phase three-level neutral-point diode-clamped (NPC) multilevel inverter (MLI). A widespread space-vector pulse width modulation (SVPWM) technique to mitigate the perpetual problem of the NPC-MLI, the CMV, proposed. The proposed scheme is an effectual blend of nearest three vector (NTV) and selected three vector (STV) techniques. This scheme is capable to reduce the CMV without compromise the inverter output voltage and Total harmonics distraction (THD). CMV reduction achieved less than +Vdc/6 using the proposed vector selection procedure. The theoretical Investigations, the MATLAB software based computer simulation and Field Programmable Gate Array (FPGA) supported hardware corroboration have shown the superiority of the proposed technique over the conventional SVPWM schemes.

scholarly journals A New Approach to the PWM Modulation for the Multiphase Matrix Converters Supplying Loads with Open-End Winding

Energies ◽  
2021 ◽  
Vol 14 (2) ◽  
pp. 466
Author(s):  
Pawel Szczepankowski ◽  
Natalia Strzelecka ◽  
Enrique Romero-Cadaval
Keyword(s):  
Pulse Width Modulation ◽  
Harmonic Distortion ◽  
Simulation Software ◽  
Common Mode ◽  
New Approach ◽  
Matrix Converters ◽  
Load Voltage ◽  
Common Mode Voltage ◽  
The Common ◽  
Open End Winding

This article presents three variants of the Pulse Width Modulation (PWM) for the Double Square Multiphase type Conventional Matrix Converters (DSM-CMC) supplying loads with the open-end winding. The first variant of PWM offers the ability to obtain zero value of the common-mode voltage at the load’s terminals and applies only six switches within the modulation period. The second proposal archives for less Total Harmonic Distortion (THD) of the generated load voltage. The third variant of modulation concerns maximizing the voltage transfer ratio, minimizing the number of switching, and the common-mode voltage cancellation. The discussed modulations are based on the concept of sinusoidal voltage quadrature signals, which can be an effective alternative to the classic space-vector approach. In the proposed approach, the geometrical arrangement of basic vectors needed to synthesize output voltages is built from the less number of vectors, which is equal to the number of the matrix converter’s terminals. The PWM duty cycle computation is performed using only a second-order determinant of the voltages coordinate matrix without using trigonometric functions. A new approach to the PWM duty cycles computing and the load voltage synthesis by 5 × 5 and 12 × 12 topologies has been verified using the PSIM simulation software.

scholarly journals Optimization of TSPWM for Common-Mode Voltage Reduction in Vehicular Electric Drive System

2021 ◽  
Vol 13 (1) ◽  
pp. 5
Author(s):  
Shang Jiang ◽  
Yuan Wang
Keyword(s):  
Electric Drive ◽  
Drive System ◽  
Modulation Method ◽  
Time Interval ◽  
Common Mode ◽  
Common Mode Voltage ◽  
Electric Drive System ◽  
The Common ◽  
Modulation Methods ◽  
Zero Voltage

Common-mode voltage can be reduced effectively by optimized modulation methods without increasing additional costs. However, the existing methods cannot satisfy the requirements of the vehicular electric-drive application. This paper optimizes the tri-state voltage modulation method to reduce the common-mode voltage for vehicular electric drive system applications. Firstly, the discontinuous switching issue during sector transition is analyzed. Under the limit of two switching times in one period, multiple alignments combination is proposed to address that issue. Secondly, the zero-voltage time intervals in different modulation ranges are explored. This paper proposes an unsymmetric translation method to reconstruct the voltage vector, and then the minimum zero-voltage time interval is controlled to enough value for safe switching. Finally, the proposed methods have been validated through experiments on a vehicular electric drive system. The results show that the common-mode voltage can be reduced effectively in the whole range with the optimized tri-state voltage modulation method.

scholarly journals Investigations on EMI Mitigation Techniques: Intent to Reduce Grid-Tied PV Inverter Common Mode Current and Voltage

Energies ◽  
2019 ◽  
Vol 12 (17) ◽  
pp. 3395 ◽  
Author(s):  
Umashankar Subramaniam ◽  
Sagar Mahajan Bhaskar ◽  
Dhafer J.Almakhles ◽  
Sanjeevikumar Padmanaban ◽  
Zbigniew Leonowicz
Keyword(s):  
Electromagnetic Interference ◽  
Pulse Width Modulation ◽  
Leakage Currents ◽  
Common Mode ◽  
Third Harmonic ◽  
Electrical Drives ◽  
Pv Inverter ◽  
Common Mode Voltage ◽  
Modulation Techniques ◽  
Power Inverters

Power inverters produce common mode voltage (CMV) and common mode current (CMC) which cause high-frequency electromagnetic interference (EMI) noise, leakage currents in electrical drives application and grid-connected systems, which consequently drops the efficiency of the system considerably. This CMV can be mitigated by designing suitable EMI filters and/or investigating the effects of different modulation strategies. In this paper, the effect of various modulation techniques over CMV and CMC are investigated for two-level and three-level inverters. It is observed that the modified third harmonic injection method reduced the CMV and CMC in the system by 60%. This modified pulse width modulation (PWM) technique is employed along with EMI chokes which results in reduced distortion of the system.

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